Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-09-20
2003-12-30
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C365S049130
Reexamination Certificate
active
06671779
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten.
2. Description of the Prior Art
A cache may be arranged to store data and/or instructions fetched from a memory so that they are subsequently readily accessible by a processor. Hereafter, the term “data value” will be used to refer to both instructions and data. The cache will store the data value until it is overwritten by a data value for a new location required by the processor. The data value is stored in cache using either physical or virtual memory locations. Should the data value in the cache have been altered then it is usual to ensure that the altered data value is re-written to the memory, either at the time the data is altered or when the data value in the cache is overwritten.
A number of different configurations have been developed for organising the contents of a cache. One such configuration is the so-called high associative cache. In an example 16 Kbyte high associative cache such as the 64-way set associative cache
30
illustrated in
FIG. 1A
, each of the 64 ways
110
contains a number of cache lines
130
. Data values associated with a particular virtual address can be stored in a particular cache line of any of the 64 ways
110
(i.e. there are 64 choices of location for that data value within the cache
30
). Each such group of 64 cache lines is referred to as a set. Each way
110
stores 256 bytes (16 Kbyte cache/64 ways). If each cache line stores eight 32-bit words then there are 32 bytes/cache line (8 words×4 bytes/word) and 8 cache lines in each way ((256 bytes/way)/(32 bytes/cache line)).
Another such configuration is the so-called low associative cache. In an example 16 Kbyte low associative cache such as the 4-way set associative cache
30
′ illustrated in
FIG. 1B
, each of the 4 ways
140
,
142
,
144
,
146
contain a number of cache lines
130
. Data values associated with a particular virtual address can be stored in a particular cache line of any of the 4 ways (i.e. each set has 4 cache lines). Each way stores 4 Kbytes (16 Kbyte cache/4 ways). If each cache line stores eight 32-bit words then there are 32 bytes/cache line (8 words×4 bytes/word) and 128 cache lines in each way ((4 Kbytes/way)/(32 bytes/cache line)).
A data value stored in the cache may be overwritten to allow a data value for a new location requested by the processor to be stored. If the data value overwritten is then required for a subsequent operation it must be re-fetched from the main memory which may take a number of clock cycles. Hence, when it is known that certain data values stored in the cache will be required for a future operation it is useful to designate those data values stored in the cache as locked to prevent those data values from being overwritten, this technique often being referred to as “lockdown”. By locking the data value it is possible to ensure that the data value will be in the cache when it is required, which provides, for example, predictability of access times for real-time code.
FIG. 2
illustrates one such lockdown technique of the 4-way set associative cache
30
′ described above which utilises a cache controller
20
. The cache controller
20
selects one of the four ways
140
,
142
,
144
,
146
in the cache
30
′ to store the fetched data value. Typically, when storing data values in the cache, a so-called “linefill” technique is used whereby a complete cache line of, for example, 8 words (32 bytes) will be fetched and stored. The cache controller
20
comprises a locked way register
22
and force bit flag
24
. The locked way register
22
determines the number of ways
140
,
142
,
144
,
146
that are used to store locked data. If data values are to be locked in the cache, the force bit flag
24
is set, whereas if data values are not to be locked in the cache, the force bit flag
24
is reset.
When a data value is to be stored in the cache
30
′, the cache controller
20
will determine the status of the locked way register
22
and force bit flag
24
. If the force bit flag
24
is not set then cache controller
20
will select one of the unlocked ways and the data value is stored in a suitable location in the unlocked way.
However, when lockdown is required the locked way register
22
is set to select the way to be locked and the force bit flag
24
is set. Now that the force bit flag
24
is set the cache controller
20
selects the locked way in dependence on the contents of the locked way register
22
and the data value is stored in a suitable location within the locked way. For example, assuming the locked way register
22
contains a value “0”, line fills of locked data values will occur in way
0
. Once lockdown is complete, the locked way register is incremented, in this example to contain a value “1”, and the force bit flag
24
is reset. Data values stored in way
0
are now locked. Any further data values to be stored will be placed in ways
1
to
3
. Should further data values need to be locked in the cache, the force bit flag
24
is set and line fills of locked data values will then occur in way
1
. Again, once lockdown is complete, the locked way register is incremented, in this example to contain a value “2”, and the force bit flag
24
is reset. Data values stored in way
0
and way
1
are now locked.
As described above, should data values need to be stored in an unlocked way, the cache controller
20
will select one of the remaining unlocked ways for fetched data to be stored thereafter. Hence, lockdown is achieved and the locked data values cannot be overwritten without the force bit flag
24
being set.
Whilst the lockdown technique described above allows lockdown, this approach has a number of disadvantages.
Firstly, it is clear that this technique is not very flexible as during lockdown sequential ways are filled with locked data values and hence, for example, if way
1
contains locked data values, way
0
cannot be arranged to store unlocked data values without way
1
also being so arranged.
Secondly, the lockdown technique requires a dedicated lockdown program to carefully manage the storage of data values in the lockdown way to ensure that parts of the lockdown program do not get locked in the lockdown way along with the data. Having the lockdown program or parts thereof occupying the lockdown way is clearly undesirable as this will result in incorrect operation of the lockdown process. Hence, the lockdown program will either need to be written such that it resides in an area of so-called “uncacheable” memory such that the lockdown program does not get locked in the cache, or will have to be pre-loaded into another cache way prior to performing the lockdown process. Furthermore, when the dedicated program is forced to operate from memory, its operation is comparatively slow.
Hence, there is a need to provide an improved lockdown technique.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a data processing apparatus comprising a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers, each lockdown controller being associated with a corresponding way, each lockdown controller comprising an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way.
In accordance with embodiments of the present invention, only d
ARM Limited
Chace Christian P.
Sparks Donald
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