Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-07-06
2003-05-13
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S143000, C711S133000, C711S156000
Reexamination Certificate
active
06564301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be associated with different types of memory region, and where the technique used to synchronise the contents of the cache with corresponding entries in the memory differs dependent on the memory region.
2. Description of the Prior Art
A cache may be arranged to store data and/or instructions so that they are subsequently readily accessible by a processor. Hereafter, the term “data value” will be used to refer to both instructions and data.
A number of different techniques have been developed for synchronising the contents of a cache with the contents of a memory, such as an off-chip main memory. For example, data values in the cache may be from a “write through” region of memory, in which case whenever a data value stored in a cache line is updated by a new data value, then that new data value is also at that time output to memory, thereby maintaining synchronisation between the data values in the cache and the data values in the memory.
Another known type of memory region is referred to as a “write back” region. If a cache is arranged to store data values from a write back memory region, then when a data value in a cache line is updated by a new data value, a “dirty bit” associated with that cache line is set to indicate that the data value has been updated. However, no action is taken at that time to update the entry in the memory. Then, when that cache line is flushed from the cache, for example to make way for a different data value to be stored in the cache, then the “dirty bit” is evaluated to determine whether any data values stored at that cache line have been updated, and if so, the data values in the cache line are then output to the memory for storage to maintain coherency.
It is becoming common to allow a cache to store data values from different regions of memory, and hence the synchronization technique employed for any particular entry in the cache will depend on the memory region associated with that entry. Hence, for example, for some data values in the cache the above-mentioned write back technique may need to be employed, whilst for other data values in the cache, the above-mentioned write through technique may need to be employed.
Whilst this development provides improved flexibility, it increases the overhead required to effectively manage the cache. In particular, when the cache determines that a new data value output by the processor core is to update a data value at a particular cache line, a protection unit provided within the data processing apparatus needs to determine in which memory region that data value is contained, and to notify the cache accordingly to ensure that the cache correctly updates the cache line. For example, if the data value is in a write through region, then the dirty bit should not be set, since the new data value will also be provided directly to the memory for storage. In contrast, if the data value is in a write back region, then the dirty bit should be set, since the new data value will not be provided directly to the memory for storage, but will only be provided later when that data value is flushed from the cache.
It has been found that the time taken by the protection unit to provide this information to the cache adversely affects the speed with which the cache can be updated, this having a knock-on effect on the efficiency of the processor core, since typically the processor core cannot begin processing the next instruction until the update to the cache has occurred.
It will be appreciated that the protection unit can be embodied as a specific logical element for controlling access to memory regions, or alternatively the function of the protection unit can be provided by a more complex logical element such as a Memory Management Unit (MMU) which can be arranged to perform additional functions. For the purposes of the present application, both of the above will be referred to as a protection unit.
It is an object of the present invention to provide an improved technique for managing caches.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a data processing apparatus, comprising: a cache having a plurality of cache lines for storing data values retrieved from a plurality of memory regions of a memory, a first memory region being such that when a data value from that first memory region is stored in the cache and is subsequently updated within the cache by a new data value, the new data value is not transferred to memory until that new data value is removed from the cache; a marker associated with each cache line and being settable to indicate that the data values stored in the corresponding cache line are from said first memory region; a protection unit for determining control parameters for controlling the transfer of data values between the cache and the memory, and being arranged, when said data values are to be loaded from the memory into a cache line of the cache, to determine whether said data values are from said first memory region and to cause the marker to be set accordingly; and a processor core arranged to output a new data value for storage; the cache being arranged to determine if the new data value output by the processor core is to replace a data value stored in a cache line of the cache, and if so to update the corresponding cache line with the new data value, and to apply predetermined criteria to determine whether to set an update identifier indicating that the data value has been updated by the new data value, such that when the new data value is subsequently removed from the cache it can be determined whether to transfer that new data value to the memory.
In accordance with the present invention, a marker is associated with each cache line, which is settable to indicate that the data values stored in the corresponding cache line are from a first memory region, and the protection unit is then adapted to determine whether those data values are in the first memory region at the time that that cache line is initially loaded with those data values from memory, and to cause the marker to be set accordingly. By this approach, when the corresponding cache line is updated with a new data value, the cache can apply predetermined criteria to determine whether to set an update identifier indicating that the data value has been updated, without having to wait for any input from the protection unit. This approach effectively removes the critical path of deciding at the time of the cache line update whether the data value is in the first memory region, and thus the efficiency of the data processing apparatus can be significantly improved.
The new data value output by the processor core may be derived from the corresponding data value as previously stored, or may be an entirely new data value derived without reference to the corresponding data value as previously stored. The data value is considered here to be ‘new’ in the sense that it is more recent than the data value for that address stored in either the cache or the memory.
The predetermined criteria applied by the cache at the time of updating the cache line can take a number of different forms. In one embodiment, the predetermined criteria identify that the update identifier should be set if the marker is set, whereby when the new data value is subsequently removed from the cache, the update identifier is used to determine whether to transfer that new data value to the memory. Considering the earlier example of a memory containing both a write back region and a write through region, this approach ensures that the update identifier is only set when new data values stored in the cache are from the write back region of memory, the update identifier not being set when new data values stored in the cache are from the write through region. Hence, the result is the same as that which would be achieved using the earlier id
Anderson M. D.
ARM Limited
Kim Matthew
Nixon & Vanderhye P.C.
LandOfFree
Management of caches in a data processing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Management of caches in a data processing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Management of caches in a data processing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3007548