Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-03-29
2008-10-07
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S122000
Reexamination Certificate
active
07434007
ABSTRACT:
The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory. When employing exclusive behavior, the n-th level cache memory is operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory. This has been found to reduce the frequency of evictions of lines from the n+1-th level cache memory when employing exclusive behaviour.
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Y. Zheng et al., “Performance Evaluation of Exclusive Cache Hierarchies”, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS04), Mar. 2004, pp. 89-96.
Airaud Cédric Denis Robert
Evrard Christophe Philippe
Raphalen Philippe Jean-Pierre
ARM Limited
Dare Ryan
Kim Matt
Nixon & Vanderhye P.C.
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