Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-10-05
2004-05-25
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S165000, C365S185110, C714S006130, C714S718000
Reexamination Certificate
active
06742078
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to management, a data link structure and a calculating method for a flash memory, and especially to establishment of a corresponding relationship between a logic block address and a real access address in order to ensure completeness in a data link. Furthermore, the invention provides protection against power failure to protect the data link structure and improve stability in use of the flash memory.
A flash memory is a semiconductor storage device which features high storage capacity per unit density, high write speed, and easiness to carry about. It is very suitable for communication apparatuses with light weight and small dimensions. In addition, it is possible to retain data without use of a battery, and therefore, flash memories have become accepted by users in a short period of time. However, the flash memory has some shortcomings, such as a restricted erase/program frequency. According to the specifications of the flash memory, normal operation of a block (8192 bytes—the smallest unit for easy operation of the flash memory) will not be able to be ensured if the erase frequency exceeds 1 million times.
Therefore, in view of the erase frequency restriction, the design of a better calculating method and data link structure, which is able to allot the erase/program frequency evenly to each block without any influence on the speed of data access and operation, and to ensure the completeness in data access, would be desirable. How to meet all the requirements mentioned above at the same time has been a tough task for firmware designers of flash memories.
SUMMARY OF THE INVENTION
The major object of the present invention is to provide a data link structure and calculating method for a flash memory so that the flash memory will be able to be used effectively. The data link structure and the calculating method are inseparable. The invention provides for division of the flash memory, establishment of the data link structure, management and paging of a spare block, and write procedures in the flash memory so that the time for data searching and data writing can be saved effectively, and so that the service life of the flash memory may be prolonged.
REFERENCES:
patent: 5283790 (1994-02-01), Kawashita
patent: 5630093 (1997-05-01), Holzhammer et al.
patent: 5898868 (1999-04-01), Krueger et al.
patent: 5978808 (1999-11-01), Wells et al.
patent: 6212097 (2001-04-01), Kihara et al.
patent: 6237110 (2001-05-01), Lin et al.
patent: 6360293 (2002-03-01), Unno
patent: 6412080 (2002-06-01), Fleming et al.
patent: 6412089 (2002-06-01), Lenny et al.
patent: 6427186 (2002-07-01), Lin et al.
patent: 6477616 (2002-11-01), Takahashi
patent: 6535995 (2003-03-01), Dobbek
Chien Cheng-Chih
Lee Chin-Chen
Ng Soo Ching
Pua Khein Seng
Yang Jiunn-Yeong
Bataille Pierre-Michel
Feiya Technology Corp.
Rabin & Berdo P.C.
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