Majority voting logic circuit for dual bus width

Details Majority voting logic circuit for dual bus width Majority voting logic circuit for dual bus width

2008-07-01

2011-11-29

Baker, Stephen (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S811000

Reexamination Certificate

active

08069403

ABSTRACT:
A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.

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