Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-09
2003-09-09
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C707S793000, C707S793000
Reexamination Certificate
active
06618833
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the specification and development of systems and processors, and in particular to the maintenance of data defining a system model.
BACKGROUND OF THE INVENTION
Traditional design flows for processors and systems involve the production of an architectural specification from which all design and development is based. This architectural specification is, typically, either a written specification or an executable “golden” model written in some programming language. The main problem with this approach is that when dealing with such complex system it is extremely unlikely that the specification will be correct first time. Inevitably, for a substantial period of the project, changes will be required as feedback is received from, among others, marketing, customers, hardware designers and software developers. This requires changes in the specification which, once agreed, need to propagate to all the groups reliant upon it, for example: modelling, micro-architecture, verification, toolchain, OS, applications and documentation. This update process will happen many times in the lifecycle of a project and is usually performed manually by each group; an approach which is slow, error-prone and labour intensive.
It is an aim of the invention to reduce the time, cost and errors associated with iterating the architectural specification of a device.
SUMMARY OF THE INVENTION
According to one aspect of the invention there is provided a method of operating a computer to generate a set of electronic data defining a system model from an architecture database which is configured to hold in an electronic storage medium architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key, the method comprising: reading the primary key for each architectural parameter; generating in an electronic storage medium a structured definition entry of the architectural parameter in an electronically readable format, the structured definition entry being associated with an identification field defining the parameter; and loading the primary key into the identification field and the subsidiary data into the structured definition file.
According to another aspect of the invention there is provided a method of designing a processor comprising: defining a processor specification and generating from the processor specification architectural parameters implementing the specification; loading the architectural parameters into an electronic storage medium to create an architectural database which is configured to hold in an electronic storage medium architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key; creating in an electronically readable medium text in a humanly readable format defining the architectural parameters in a structured tabular format wherein a table title holds the primary key for each architectural parameter; modifying the processor specification and effecting manually consequential modification to the architectural parameters in the text; and using a translation tool in the form of a program executed by a computer to automatically transfer the modification into the database by locating any new or modified tables in the tabular format and loading the table title into the primary key field and other data in the table into the set of fields for subsidiary data in a predetermined manner.
According to another aspect of the invention there is provided a method of designing a processor comprising: defining a processor specification and generating from the processor specification architectural parameters implementing the specification; loading the architectural parameters into an electronic storage medium to create an architectural database which is configured to hold architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key; creating in an electronically readable medium text in a humanly readable format defining the architectural parameters in a structured tabular format wherein a table title holds a primary key for each architectural parameter; modifying the processor specification and effecting manually consequential modifications to the architectural parameters in the architectural database; and using a translation tool in the form of a program executed by a computer to automatically transfer the modifications into the text from the database by loading the contents of the primary key field and subsidiary fields into the structured tabular format.
Thus, the structural definition entries can be tables used to generate readable text or programming definitions for generating modelling views.
Automating the distribution of architectural data dramatically reduces the impact of changes in the specification on project time scales. For example, with the use of appropriate views, it is simpler to keep the toolchain (compiler, assembler, linker and simulator) in step with each other and the specification.
As there is a reduction in the amount of manually replicated architectural data produced in different groups, inconsistencies are far less likely to creep in.
The quality of the written specification should improve for a number of reasons.
The translation tools can be arranged to carry out “sanity checks” on the architectural data flowing from, or to, the written specification, thus reducing errors.
Consistency is improved as the automation ensures that similar types of information, for example, register descriptions are presented in the same way.
Clarity can be improved by being free to present the same information in different ways without the possibility of inconsistencies arising. For example, giving opcode information as part of an instruction description as well as in an opcode summary table.
REFERENCES:
patent: 5553218 (1996-09-01), Li et al.
patent: 5557774 (1996-09-01), Shimabukuro et al.
patent: 5615367 (1997-03-01), Bennett et al.
patent: 5734887 (1998-03-01), Kingberg et al.
patent: 5848263 (1998-12-01), Oshikiri
patent: 6237003 (2001-05-01), Lewish et al.
patent: 6356897 (2002-03-01), Gusack
patent: 0463301 (1992-01-01), None
patent: 0 847 022 (1998-06-01), None
Ghosh, I. et al., “A design for testability technique for register transfer level circuits using control/data flow extraction”, IEEE, pp. 706-723.*
Standard Search Report from application No. RS102362.
Ibbett R. N. et al.,Hase: A Flexible Toolset for Computer Architects, Computer Journal, vol. 38, No. 10, Jan. 1, 1995, pp. 755-764, XP000584673.
British Search Report from patent application No. 9828795.6, filed Dec. 29, 1998.
Agterkamp Hendrick-Jan
Hill Mark
Sturges Andrew
Morris James H.
Niebling John F.
Skrivanek, Jr. Robert A.
STMicroelectronics Limited
Whitmore Stacy
LandOfFree
Maintenance of a system model does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Maintenance of a system model, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Maintenance of a system model will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3111878