Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-12
2011-04-12
Doan, Duc T (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07925837
ABSTRACT:
A method, computer program product and computer system for maintaining write cache and parity update footprint coherency in a multiple storage adaptor configuration for storage adaptors in a storage subsystem, which includes providing atomic updating of the storage adaptors and the attached disk drives, enabling runtime addition and runtime subtraction of a storage adaptor in the multiple storage adaptor configuration, and maintaining write cache and parity update footprint coherency using atomic updating, runtime addition and runtime subtraction of a storage adaptor.
REFERENCES:
patent: 6539463 (2003-03-01), Kuwata
patent: 7657781 (2010-02-01), Dixon et al.
patent: 2003/0023808 (2003-01-01), Bakke et al.
patent: 2006/0112032 (2006-05-01), Bakke et al.
patent: 2007/0028136 (2007-02-01), Forhan et al.
Edwards Joseph Roger
Galbraith Robert Edward
Gerhard Adrian Cuenin
Larson Timothy James
Maitland, Jr. William Joseph
Doan Duc T
International Business Machines - Corporation
Rabin & Berdo PC
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