Maintaining uniform CMP hard mask thickness

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S692000, C257SE21577

Reexamination Certificate

active

10711145

ABSTRACT:
A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

REFERENCES:
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patent: 6358839 (2002-03-01), Li et al.
patent: 6479391 (2002-11-01), Morrow et al.
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patent: 2002/0182853 (2002-12-01), Chen et al.
L.P. Allen et al., Substrate Smoothing Using Gas Cluster Ion Beam Processing, 2001, Journal of Electronic Materials, vol. 30, No. 7, (Abstract only).

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