Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-27
2003-04-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C361S737000, C361S760000
Reexamination Certificate
active
06553555
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer memory systems, and more particularly, to a method and apparatus for routing signal paths on a printed circuit board for high speed DRAM requiring low signal path impedance.
2. Description of the Related Art
Competitive pressure and customer demand in the computer industry is currently forcing computer manufacturers to lower cost, reduce size, and increase performance of their products. Currently, all Pentium and higher-grade buses operate in the range of at least 66 MHz up to 300 MHz. As operating systems and application programs have grown, so has the need for more memory that operates at faster speed. Dynamic random-access memory (DRAM) manufacturers have continued to improve the cost, speed, and density of their chips using various configurations such as fast page mode (FPM) DRAM chips capable of reaching a maximum frequency of 28.5 MHz within a given page of memory, extended-data-out (EDO) DRAM which achieves a maximum frequency of 40 MHz, and synchronous DRAM (SDRAM) and burst EDO (BEDO) DRAM capable of burst rates up to 100 MHz. Higher speed buses capable of data transfer rates in the gigahertz range are planned to be introduced in the near future. Ideally, the memory must supply data to the processor at the same speed as the processor's system clock. Thus, there is a need to further improve DRAM speed over current capabilities.
Two new memory designs, SyncLink and Rambus, address current and near-future memory speed and bandwidth needs. SyncLink is a consortium of DRAM manufacturers which have proposed a draft standard to the IEEE for a uniform memory architecture that will evolve over several iterations. The SyncLink standard is royalty-free and open to all. The proposal calls for a command-driven, packet-oriented bus operating up to 800 MHz, with a 16-bit wide data path. Rambus is a high-speed DRAM subsystem, known as Direct Rambus, that is currently capable of transferring data at speeds of 1.6 gigabytes per second. Direct Rambus memory modules, known as RIMM modules, use standard industry assemblies similar to those of dual in-line memory modules (DIMMs). The subsystem consists of the RAM, the RAM controller, and the bus (channel) connecting the RAM to the microprocessor and devices in the computer that use it.
It is likely that additional high-speed memory modules will be developed in the future. High-speed RAM is expected to accelerate the growth of visually intensive interfaces such as 3-D, interactive games, and streaming multimedia. Much faster data transfer rates from attached devices such as videocams using firewire and the accelerated graphics port (AGP) make it important to reduce the bottleneck in getting data into the computer, staging it in RAM, and moving it through the microprocessor and to the display or other output devices. Traditionally, digital system designers could develop systems without much regard to board layout issues such as trace length, width, impedance, capacitive loading, and routing. But as digital systems are pushed to higher frequencies, these issues become increasingly critical. Thus, it is necessary to provide a printed circuit board (PCB) layout that is capable of meeting the performances requirements of high-speed memory modules as they are developed and integrated in state-of-the-art computer systems.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, there is provided an apparatus for coupling a memory controller and a memory module in electrical communication. A plurality of data signal paths are formed on a circuit board. Each data signal path being operable to conduct an electrical data signal between the memory controller and the memory module. A plurality of non-data signal paths are also formed on the circuit board. The pinout of a connector for coupling the memory controller and the memory module is designed so that at least one of the non-data signal is positioned beside each data signal. As a result, non-data signal paths are positioned beside each data signal path, thereby forming guard bands on both sides of the data signal paths.
The circuit board includes a plurality of contacts that are operable to conduct electric signals and are typically used to plug in connectors for devices such as memory modules. In the present invention, the data signal paths are routed between the contacts on the circuit board so as to avoid the contacts. Each non-data signal path is routed through the contacts on one side of a corresponding data signal path. Each non-data signal path conducts the same electrical signal as the contacts through which it is routed.
The guard bands formed on both sides of the data signal paths help insure the impedance level, current return path, and shielding required by the data signal path, even on a densely perforated circuit board such as a motherboard. To further maintain circuit impedance within desired tolerances, the width of the data signal paths is substantially constant along the length of the data signal path, and the non-data signal paths are substantially parallel to the data signal paths.
In another embodiment, the memory module includes at least one memory chip mounted on a connector card. A connector is used to mate the connector card with the circuit board. The connector includes a plurality of paths corresponding to the data signal paths and the non-data signal paths, so that signals may be transmitted between the memory controller and the memory chip. The non-data signal paths are either ground signal paths, power signal paths, or a combination of ground and power signal paths, depending on the memory controller's signal requirements.
In another embodiment, the memory module includes at least one memory chip mounted on a connector card. A connector is used to mate the connector card with a memory expansion card (MEC). The MEC plugs into the circuit board. The connector, the connector card, and the MEC include a plurality of paths corresponding to the data signal paths and the non-data signal paths, so that signals may be transmitted between the memory controller and the memory chip. The non-data signal paths are either ground signal paths, power signal paths, or a combination of ground and power signal paths, depending on the memory controller's signal requirements.
The present invention is particularly suitable for use with high-speed DRAM modules, such as the Rambus DRAM module, where strict impedance tolerances are imposed along the data signal paths. The present invention is also suitable in any application where guard banding is used to help control the impedance level, current return path, and shielding required by the data signal path, even when signal paths are routed through densely populated environments.
The foregoing has outlined rather broadly the objects, features, and technical advantages of the present invention so that the detailed description of the invention that follows may be better understood.
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Green D. Scott
Lash Steven J.
Baker & Botts L.L.P.
Dell Products L.P.
Malsawma Lex H.
Smith Matthew
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