Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-06-28
2011-06-28
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S205000, C711S206000, C711S207000, C711S119000, C717S136000, C717S137000
Reexamination Certificate
active
07971002
ABSTRACT:
Methods and systems for maintaining instruction coherency in a translation-based computer system architecture are described. A translation coherence cache memory can be used to store a memory page reference that identifies a memory page. The cache memory also stores a permission bit corresponding to the memory page reference. The permission bit indicates whether the memory page comprises code that has been translated into another form.
REFERENCES:
patent: 5345576 (1994-09-01), Lee et al.
patent: 5412787 (1995-05-01), Forsyth et al.
patent: 5623633 (1997-04-01), Zeller et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5704058 (1997-12-01), Derrick et al.
patent: 5761468 (1998-06-01), Emberson
patent: 5860111 (1999-01-01), Martinez et al.
patent: 5897656 (1999-04-01), Vogt et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 5987571 (1999-11-01), Shibata et al.
patent: 6088769 (2000-07-01), Luick et al.
patent: 6122714 (2000-09-01), VanDoren et al.
patent: 6128701 (2000-10-01), Malcolm et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6164841 (2000-12-01), Mattson et al.
patent: 6199152 (2001-03-01), Kelly et al.
patent: 6205517 (2001-03-01), Sugaya
patent: 6219745 (2001-04-01), Strongin et al.
patent: 6345320 (2002-02-01), Kawamata et al.
patent: 6430657 (2002-08-01), Mittal et al.
patent: 6438653 (2002-08-01), Akashi et al.
patent: 6446187 (2002-09-01), Riedlinger et al.
patent: 6535960 (2003-03-01), Nishida et al.
patent: 6546464 (2003-04-01), Fortuna et al.
patent: 6594821 (2003-07-01), Banning et al.
patent: 6633958 (2003-10-01), Passint et al.
patent: 6638653 (2003-10-01), Andou et al.
patent: 6662277 (2003-12-01), Gaither
patent: 6668287 (2003-12-01), Boyle et al.
patent: 6691306 (2004-02-01), Cohen et al.
patent: 6751706 (2004-06-01), Chauvel et al.
patent: 6785780 (2004-08-01), Klein et al.
patent: 6868481 (2005-03-01), Gaither et al.
patent: 6925536 (2005-08-01), Glasco et al.
patent: 2003/0005234 (2003-01-01), Sperber et al.
patent: 2003/0005237 (2003-01-01), Dhong et al.
patent: 2003/0131202 (2003-07-01), Khare et al.
patent: 2003/0163745 (2003-08-01), Kardach
patent: 2006/0123172 (2006-06-01), Herrell et al.
Agarwal et al., An Evaluation of Directory Schemes for Cache Coherence, ISCA, May 30-Jun. 2, 1988, pp. 280-289.
Jouppi, Norman P., Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proceedings of the 17th Annual International Symposium on Computer Architecture, at 388-397 (IEEE 1990).
Jim Handy, The Cache Memory Book, 1998, Academic Press, 2nd edition, p. 157.
Agarwal et al., The MIT Alewife Machine, Mar. 1999, Proceedings of the IEEE, vol. 87, No. 3, pp. 430-444.
CPU Cache. http://en.wikipedia.org/wiki/CPU—cache#Exclusive—versus—inclusive. Wikipedia, the free encyclopedia. Jan. 8, 2009.
Non Final Office Action; Mail Date Apr. 7, 2008; U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Jun. 12, 2009; U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Aug. 26, 2008; U.S. Appl. No. 11/439,361.
Notice of Allowance, Mail Date Dec. 12, 2008; U.S. Appl. No. 11/439,361.
Restriction Requirement, Mail Date Feb. 21, 2008; U.S. Appl. No. 11/439,361.
Final Office Action, Mail Date Feb. 25, 2009; U.S. Appl. No. 11/102,289.
Final Office Action, Mail Date Sep. 28, 2007; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date Mar. 23, 2007; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date May 12, 2009; U.S. Appl. No. 11/102,289.
Non Final Office Action, Mail Date Jun. 12, 2008; U.S. Appl. No. 11/102,289.
Final Office Action, Mail Date Mar. 16, 2009; U.S. Appl. No. 11/102,171.
Final Office Action, Mail Date Nov. 26, 2007; U.S. Appl. No. 11/102,171.
Non Final Office Action, Mail Date Mar. 26, 2007; U.S. Appl. No. 11/102,171.
Non Final Office Action, Mail Date Jul. 9, 2008; U.S. Appl. No. 11/102,171.
Non Final Office Action, Mail Date Jul. 27, 2006; U.S. Appl. No. 10/411,168.
Non Final Office Action, Mail Date Sep. 20, 2005; U.S. Appl. No. 10/411,168.
Non Final Office Action, Mail Date Nov. 1, 2007; U.S. Appl. No. 10/411,168.
Notice of Allowance, Mail Date Mar. 19, 2009; U.S. Appl. No. 10/411,168.
Notice of Allowance, Mail Date Apr. 12, 2007; U.S. Appl. No. 10/411,168.
Notice of Allowance, Mail Date May 23, 2008; U.S. Appl. No. 10/411,168.
Notice of Allowance, Mail Date Oct. 30, 2008; U.S. Appl. No. 10/411,168.
Restriction Requirement, Mail Date Mar. 28, 2006; U.S. Appl. No. 10/411,168.
Notice Of Allowance; Mail Date Aug. 6, 2009; U.S. Appl. No. 10/411,168.
Notice Of Allowance; Mail Date Jun. 26, 2009; U.S. Appl. No. 11/439,361.
Notice Of Allowance; Mail Date Mar. 12, 2009; U.S. Appl. No. 11/439,361.
Final Office Action; Mail Date May 10, 2010; U.S. Appl. No. 11/102,171.
Anant Agarwal; et al. “The MIT Alewife Machine” Laboratory for Computer Science, Massachusetts Institute of Technology Cambridge, Massachuseets 02139.
Non-Final Office Action Dated Dec. 2, 2009; U.S. Appl. No. 11/102,171.
Handy, Jim, “The Cache Memory Books”, 1998, Academic Press, 2nd Edition, pp. 89-94.
Final Office Action Dated Jan. 27, 2010; U.S. Appl. No. 11/102,289.
Non-Final Office Action Dated Jul. 29, 2010; U.S. Appl. No. 12/624,094.
Notice of Allowance Dated Dec. 23, 2010; U.S. Appl. No. 12/624,094.
Dunn David
Rozas Guillermo
Ellis Kevin L
Otto Alan
LandOfFree
Maintaining instruction coherency in a translation-based... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Maintaining instruction coherency in a translation-based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Maintaining instruction coherency in a translation-based... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2642366