Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-08-14
2007-08-14
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C709S238000, C710S052000
Reexamination Certificate
active
10458869
ABSTRACT:
A technique for maintaining order among a plurality of entities contained in an intermediate node by ensuring orderly access to a resource shared by the entities. A request is generated to access the resource. The request is placed on a queue associated with an entity. The request eventually reaches the head of the queue. An identifier generated by a gate manager is compared with an identifier associated with the queue to determine if they match. If so, the request is transferred to the resource, which processes the request. Results acquired from the resource (if any) are transferred to the entity.
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Chanak John A.
Jeter, Jr. Robert E.
Cesari and McKenna LLP
Cisco Technology Inc.
Diller Jesse
Peugh Brian R.
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