Maintaining data integrity in DRAM while varying operating volta

Details Maintaining data integrity in DRAM while varying operating volta Maintaining data integrity in DRAM while varying operating volta

1996-10-09

1998-01-27

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

365226, G11C 11401

Patent

active

057128251

ABSTRACT:
A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generation device coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

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