Maintaining data coherency between a primary memory controller a

Details Maintaining data coherency between a primary memory controller a Maintaining data coherency between a primary memory controller a

1996-10-28

1999-04-20

Beausoliel, Jr., Robert W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39518203, 711162, G06F 1120

Patent

active

058964924

ABSTRACT:
A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with a tap coupled to the interconnect. Data is transferred from the host processor to the memory in the form of data packets. First, the host processor writes to the memory by sending a data packet to the primary memory controller which then caches the data from the data packet. The backup memory controller taps the interconnect to obtain a backup copy of the data packet as the data packet is being sent from the host processor to the primary memory controller which caches the data from the backup copy of the data packet. If the primary memory controller is functional, the primary memory controller sends the data to the memory via a primary path coupling the primary memory controller to the memory. Conversely, if the primary memory controller fails, i.e., is non-functional, the backup memory controller is tasked with completing the data transfer via a backup path coupling the backup memory controller to the memory.

REFERENCES:
patent: 5574730 (1996-11-01), End, II et al.
patent: 5617425 (1997-04-01), Anderson
patent: 5712970 (1998-01-01), Arnott et al.

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