Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-07
2002-09-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06449762
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of circuit design synthesis, and more particularly to circuit design synthesis through hardware description language.
BACKGROUND OF THE INVENTION
For the design of digital circuits on the scale of VLSI (Very Large Scale Integration) technology, designers often employ computer-aided techniques. Standard languages known as Hardware Description Languages (HDL's) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing circuits using HDL compilers, designers first describe circuit elements in HDL source code and then compile the source code to produce synthesized RTL netlists. The RTL netlists correspond to schematic representations of the circuit elements. The circuits containing the synthesized circuit elements are often optimized to improve timing relationships and eliminate unnecessary or redundant logic elements. Such optimization typically involves substituting different gate types or combining and eliminating gates in the circuit, and often results in re-ordering the hierarchies and relationships between the original RTL objects and the underlying source code that produced the RTL objects.
Typical present circuit synthesis systems do not maintain correspondence between HDL source code expressions and the corresponding RTL objects after optimization of the circuit containing the RTL objects. These present systems thus do not allow identification or display of HDL source code corresponding to certain optimized circuit elements. Such loss of correspondence limits modification or debugging of circuit elements since the corresponding source code cannot be readily located.
SUMMARY OF THE INVENTION
The present invention discloses methods and apparatuses that maintain the correspondence between a text representation of a circuit element or elements and the corresponding schematic representation of the element(s) after synthesis and optimization of the circuit containing the element(s).
In one example of a method of the invention, a circuit element is described in text representation in a source code file. A first tag is assigned to the text representation. The text representation is synthesized to produce a first schematic representation of the circuit element. A second tag corresponding to the first tag is assigned to the first schematic representation of the circuit element. The circuit containing the circuit element is optimized to produce a second schematic representation of the circuit element. A third tag corresponding to the first tag is assigned to the second schematic representation.
In one particular example of a method of the invention, a text representation, such as HDL source code, of a logic circuit is displayed. Then a graphical representation (e.g. a logical gate level schematic diagram) is displayed after compiling the text representation (resulting in a first logical gate level schematic). Then this compiled, synthesized design may be optimized resulting in a second logical gate level schematic which may be displayed. A user may select a portion of the text representation prior to optimization to cause a display of a corresponding portion of the first logical gate level schematic, and after optimization, the user may select the portion of the text representation to cause a display of a corresponding portion of the second logical gate level schematic, which may differ from the first logical gate level schematic. The corresponding portions of the first and second gate level schematics may be different due to the optimization of the synthesized logic. In each case, the corresponding portions of the gate level schematic resulted from the compilation of text representation. The association between text representation and the resulting gate level schematic is maintained (preserved) through optimizations. Similarly, a user may, prior to optimization, select a portion of the first logical gate level schematic to cause a display of a corresponding portion of the text representation (which was compiled to create the selected portion of the first logical gate level schematic). After optimization, the user may select a portion of the second logical gate level schematic (which may be different from the selected portion of the first logical gate level schematic), and this selection causes the display of a corresponding portion of the text representation (which was compiled to produce a result which, after optimization, produced the selected portion of the second gate level schematic) or a display of a portion of the first logical schematic.
According to another aspect of the present invention, the logical gate level schematic may be filtered to display only some of the gates in the design, whether or not these gates are in a critical path in the circuit.
The present invention provides computer systems which are capable of performing methods of the invention, and the invention also provides computer readable material which, when executed on a digital processing system, such as a computer system, causes the system to execute one or more of the methods of the invention.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description which follows.
REFERENCES:
patent: 5555201 (1996-09-01), Dangelo
Blakely , Sokoloff, Taylor & Zafman LLP
Do Thuan
Smith Matthew
Synplicity, Inc.
LandOfFree
Maintaining correspondence between text and schematic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Maintaining correspondence between text and schematic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Maintaining correspondence between text and schematic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2821609