Main memory system and checkpointing protocol for fault-tolerant

Details Main memory system and checkpointing protocol for fault-tolerant Main memory system and checkpointing protocol for fault-tolerant

1996-07-02

1998-07-28

Palys, Joseph

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39518204, 395569, 711135, G06F 1100

Patent

active

057872430

ABSTRACT:
A mechanism for maintaining a consistent state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory via a memory bus. A shadow memory element, which includes a buffer memory and a main storage element, is also attached to this memory bus. During normal processing, data written to primary memory is also captured by the buffer memory of the shadow memory element. When a checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured in the buffer memory is then copied to the main storage element of the shadow memory element. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

REFERENCES:
patent: 3588829 (1971-06-01), Boland
patent: 3736566 (1973-05-01), Anderson et al.
patent: 3761881 (1973-09-01), Anderson et al.
patent: 3803560 (1974-04-01), DeVoy et al.
patent: 3864670 (1975-02-01), Inoue
patent: 3889237 (1975-06-01), Alferness et al.
patent: 3979726 (1976-09-01), Lange et al.
patent: 4020466 (1977-04-01), Cordi et al.
patent: 4044337 (1977-08-01), Hicks et al.
patent: 4164017 (1979-08-01), Randell et al.
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4373179 (1983-02-01), Katsumata
patent: 4393500 (1983-07-01), Imazeki et al.
patent: 4403284 (1983-09-01), Sacarisen et al.
patent: 4413327 (1983-11-01), Sabo et al.
patent: 4426682 (1984-01-01), Riffe et al.
patent: 4435762 (1984-03-01), Milligan et al.
patent: 4459658 (1984-07-01), Gabbe et al.
patent: 4484273 (1984-11-01), Stiffler et al.
patent: 4503534 (1985-03-01), Budde
patent: 4509554 (1985-04-01), Glazer et al.
patent: 4566106 (1986-01-01), Check, Jr.
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4703481 (1987-10-01), Fremont
patent: 4734855 (1988-03-01), Banatre et al.
patent: 4740969 (1988-04-01), Fremont
patent: 4751639 (1988-06-01), Corcoran et al.
patent: 4817091 (1989-03-01), Katzman et al.
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 4819232 (1989-04-01), Krings
patent: 4823261 (1989-04-01), Bank et al.
patent: 4905196 (1990-02-01), Kirrmann
patent: 4912707 (1990-03-01), Kogge et al.
patent: 4924466 (1990-05-01), Gregor et al.
patent: 4941087 (1990-07-01), Kap
patent: 4958273 (1990-09-01), Anderson et al.
patent: 4959774 (1990-09-01), Davis
patent: 4965719 (1990-10-01), Shoens et al.
patent: 4996687 (1991-02-01), Hess et al.
patent: 5123099 (1992-06-01), Shibata et al.
patent: 5157663 (1992-10-01), Major et al.
patent: 5214652 (1993-05-01), Sutton
patent: 5235700 (1993-08-01), Alaiwan et al.
patent: 5239637 (1993-08-01), Davis et al.
patent: 5247618 (1993-09-01), Davis et al.
patent: 5263144 (1993-11-01), Zurawski et al.
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5271013 (1993-12-01), Gleeson
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5293613 (1994-03-01), Hayden et al.
patent: 5301309 (1994-04-01), Sugano
patent: 5313647 (1994-05-01), Kaufman et al.
patent: 5325517 (1994-06-01), Baker et al.
patent: 5325519 (1994-06-01), Long et al.
patent: 5327532 (1994-07-01), Ainsworth et al.
patent: 5363503 (1994-11-01), Gleeson
patent: 5369757 (1994-11-01), Spiro et al.
patent: 5381544 (1995-01-01), Okazawa
patent: 5394542 (1995-02-01), Frev et al.
patent: 5398331 (1995-03-01), Huang
patent: 5408636 (1995-04-01), Santeler
patent: 5408649 (1995-04-01), Beshears et al.
patent: 5418916 (1995-05-01), Hall
patent: 5418940 (1995-05-01), Mohan
patent: 5420996 (1995-05-01), Aoyagi
patent: 5448719 (1995-09-01), Schultz et al.
patent: 5463733 (1995-10-01), Forman et al.
patent: 5485585 (1996-01-01), Huynh et al.
patent: 5488716 (1996-01-01), Schneider et al.
patent: 5495587 (1996-02-01), Comfort et al.
patent: 5495590 (1996-02-01), Comfort et al.
patent: 5504861 (1996-04-01), Crockett et al.
patent: 5530801 (1996-06-01), Kobayashi
patent: 5530946 (1996-06-01), Bouvier et al.
patent: 5557735 (1996-09-01), Pinkston, II et al.
patent: 5566297 (1996-10-01), Devarakonda et al.
patent: 5568380 (1996-10-01), Brodnax
patent: 5574874 (1996-11-01), Jones et al.
patent: 5583987 (1996-12-01), Kobayashi et al.
patent: 5630047 (1997-05-01), Wang
patent: 5644742 (1997-07-01), Shen et al.
patent: 5649136 (1997-07-01), Shen et al.
patent: 5649152 (1997-07-01), Ohran et al.
IBM Technical Disclosure Bulletin, vol. 34, No. 10A, Mar. 1992, Memory Recovery Facility for Computer Systems; pp. 341-342.
1991 IEEE, IACOPONI, 'Hardware Assisted Real-Time Rollback in the Advanced Fault-Tolerant Data Processor; pp. 269-274.
IEEE, vol. 4, No. 6, Dec. 1992, Incremental Recovery in Main Memory Database pp. 529-540, by Eliezer Levy, et al.
IEEE, No. 2, Feb. 1988, "Sequoia: A Fault-Tolerant Tightly Coupled Multiprocessor Transaction Processing," pp. 37-45, by Philip A. Berstein.
IEEE, Dec. 1991, The Diffusion Model Based Task Remapping for Distributed Real-pp. 2-11, by Morikazu Takegaki, et al.
IBM Technical Disclosure Bulletin, vol. 36, No. 08, Aug. 1993, "Efficient Cache Access Through Compression," pp. 161-165.
N.Bowen and D.Pradhan, "Processor-and Memory-Based Checkpoint and Rollback Recovery," 1993 IEEE Transactions on Computers, pp. 22-30.
Y.Lee and K.Shin, "Rollback Propagation Detection and Performance Evaluation of FTMR.sup.2 M--A Fault Tolerant Multiprocessor," 1982 IEEE Transactions on Computers, pp. 171-180.
C.Kubiak et al., "Penelope: A Recovery Mechanism for Transient Hardware Failures and Software Errors," 1982 IEEE Transactions on Computers, pp. 127-133.
A.Feridun and K.Shin, "A Fault-Tolerant Multiprocessor System with Rollback Recovery Capabilities," 1981 IEEE Transactions on Computers, pp. 283-298.
P.Lee et al., "A Recovery Cache for the PDP-11," IEEE Transactions on Computers, vol. C-29, No. 6, Jun. 1980, pp. 546-549.
International Search Report as cited in PCT Application No. PCT/US95/07168, dated Oct. 11, 1995.
M. Banatre, A. Gefflaut, C. Morin, "Scalable Shared Memory Multi-Processors: Some Ideas to Make Them Reliable".

Affiliated with

Also associated with

Rating

Main memory system and checkpointing protocol for fault-tolerant does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Main memory system and checkpointing protocol for fault-tolerant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Main memory system and checkpointing protocol for fault-tolerant will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-30389