Main memory interface for high speed data transfer

Details Main memory interface for high speed data transfer Main memory interface for high speed data transfer

1997-01-09

1998-10-13

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

395863, 395845, 395846, 395894, 395878, 711147, 711167, G06F 1337, G06F 1316

Patent

active

058227660

ABSTRACT:
An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmits the data set to the next main control logic and coupled memory, which next control logic repeats the process, and which can be continued through a number of coupled control logic units and main memories. A data set includes a header with an address range and function information. If data is to be sent from the storage controller it is appended to the header. Each storage controller compares the address range with the address range of the coupled memory, and if within the address range and for a write, will store the appended data in the header address in the coupled memory. If within the address range and for a read, each storage controller will read the data addressed in the header from the coupled memory and return the data to the storage controller. Because of the direct access these transfer occur at high data rates. The limited number of connections used in this transfer permits accessing main memories on a circuit element using this apparatus and method.

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