Main memory DRAM interface

Details Main memory DRAM interface Main memory DRAM interface

1991-07-03

1993-11-23

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Signals

36523003, G11C 700

Patent

active

052650537

ABSTRACT:
An interface is described for a memory array including a multiplicity of DRAMs organized as a partition providing data storage and data coherency storage. The interface includes a RAS controller and a CAS controller. The RAS controller resides on a first semiconductor substrate. The RAS controller receives a RAS strobe signal and generates a data RAS signal and a data coherency RAS signal. The data RAS signal has a minimum skew with respect to said data coherency RAS signal. The CAS controller resides on a second semiconductor substrate. The CAS controller receives a memory array write enable signal for selecting byte reads and byte writes, as well as a CAS strobe signal, said CAS controller generating a multiplicity of byte CAS signals and a multiplicity of byte write enable signals for said partition, said multiplicity of byte CAS signals having a minimum skew with respect to said multiplicity of byte write enable signals by minimizing skew, the interface reduces the access time of the DRAM memory array.

REFERENCES:
patent: 4916603 (1990-04-01), Ryan et al.

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