Main memory controller adapted to correct corrupted data by...

Details Main memory controller adapted to correct corrupted data by... Main memory controller adapted to correct corrupted data by...

2002-08-05

2008-08-05

Chu, Gabriel L (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S005110, C714S006130, C714S767000

Reexamination Certificate

active

07409581

ABSTRACT:
A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

REFERENCES:
patent: 4317201 (1982-02-01), Sedalis
patent: 4862463 (1989-08-01), Chen
patent: 5164944 (1992-11-01), Benton et al.
patent: 5206865 (1993-04-01), Gruender et al.
patent: 5210860 (1993-05-01), Pfeffer et al.
patent: 5235687 (1993-08-01), Bacot et al.
patent: 5313626 (1994-05-01), Jones et al.
patent: 5321697 (1994-06-01), Fromm et al.
patent: 5331646 (1994-07-01), Krueger et al.
patent: 5367669 (1994-11-01), Holland et al.
patent: 5369650 (1994-11-01), Kirk et al.
patent: 5412668 (1995-05-01), Dewey
patent: 5426744 (1995-06-01), Sawase et al.
patent: 5462456 (1995-10-01), Howell
patent: 5490155 (1996-02-01), Abdoo et al.
patent: 5493574 (1996-02-01), McKinley
patent: 5504859 (1996-04-01), Gustafson et al.
patent: 5566297 (1996-10-01), Devarakonda et al.
patent: 5588112 (1996-12-01), Dearth et al.
patent: 5590370 (1996-12-01), Asthana et al.
patent: 5611042 (1997-03-01), Lordi
patent: 5617425 (1997-04-01), Anderson
patent: 5619642 (1997-04-01), Nielson et al.
patent: 5651129 (1997-07-01), Yokote et al.
patent: 5691945 (1997-11-01), Liou et al.
patent: 5724295 (1998-03-01), Beiley et al.
patent: 5734814 (1998-03-01), Corbin et al.
patent: 5761221 (1998-06-01), Baat et al.
patent: 5778411 (1998-07-01), DeMoss et al.
patent: 5787464 (1998-07-01), Yoshizawa et al.
patent: 5831913 (1998-11-01), Kirihata
patent: 5905854 (1999-05-01), Nielson et al.
patent: 5925119 (1999-07-01), Maroney
patent: 6038680 (2000-03-01), Olarig
patent: 6041430 (2000-03-01), Yamauchi
patent: 6088330 (2000-07-01), Bruck et al.
patent: 6289471 (2001-09-01), Gordon
patent: 6546499 (2003-04-01), Challener et al.
patent: 2005/0055501 (2005-03-01), Guha et al.
Crisp, “High Bandwidth RDRAM Technology Reduces System Cost”, IEEE, 1996.
Microsoft Press Computer Dictionary Third Edition, “main memory”, Microsoft Press, 1997, p. 297.
Microsoft Press Computer Dictionary Third Edition, “primary storage”, Microsoft Press, 1997, p. 378.

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