Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1997-04-03
2001-03-20
Nguyen, Hiep T. (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S137000, C711S141000, C711S153000, C711S173000, C710S052000
Reexamination Certificate
active
06205517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a main memory control apparatus capable of realizing high-speed access to a main memory unit in a computer system.
2. Description of the Related Art
Some CPU's include cache memories storing part of the contents stored in a main memory unit, aiming at high-speed access to the main memory unit. In such a CPU, consistency or sameness of data between the cache memory and the main memory unit is maintained by a snooping function that monitors access to the main memory unit from DMA (Direct Memory Access) enable devices other than the CPU.
Some of CPU's including cache memories, however, have no snooping function. Particularly, built-in CPU's which are becoming commonly used in commercial applications incorporate cache memories for improvement of performance, but often have no snooping function for cost reduction. In those CPU's having no snooping function, consistency of stored data between a cache memory and a main memory unit is secured by software.
More specifically, CPU's can be classified into two types; i.e., performance-directed CPU's intended for application to workstations and high-level personal computers, and built-in CPU's intended for application to home game machines, electronic notebooks, etc. In general, performance-directed CPU's each have a snooping function that monitors access to a main memory unit from other CPU's or DMA enable devices, taking into account its application to a system wherein a plurality of CPU's accessing to a common memory are employed to improve performance.
The provision of the snooping function ensures consistency of data between a cache memory incorporated in the CPU and a main memory unit.
On the other hand, built-in CPU's are designed with an emphasis placed on cost performance, because apparatus and equipment utilizing such built-in CPU's are relatively inexpensive. Accordingly, those CPU's incorporate cache memories for improvement of performance, but many of them have no snooping function for cost reduction. Because of versatility in applications, the built-in CPU's occupy a great proportion in the total number of CPU's brought to the market.
In the CPU's incorporating cache memories but having no snooping function, as mentioned above, consistency of data between a cache memory and a main memory unit is secured by software. The following two methods are known so far for achieving it.
(1) Any cache memory is not employed, or a storage area of the main memory unit, which is accessed by DMA enable devices other than the CPU, is allocated to an address area from which data cannot be loaded into the cache memory in the CPU.
(2) A storage area which is accessed by DMA enable devices is allocated to an address area from which data can be loaded into the cache memory in the CPU. But if data in a main storage area which is accessed by the DMA enable devices exits in the cache memory at the DMA start-up, the data in the cache memory is invalidated.
However, the above method (1) is disadvantageous in that since CPU access to all the area of the main memory unit or the area thereof which is accessed by DMA enable devices is made directly to the main memory unit, an access time is longer than that required to make access to the cache memory.
Also, in the above method (2), it is probable that each time write access to the main memory unit is made at the DMA start-up, the contents of the cache memory are invalidated. This results is disadvantages of reducing utilization of the cache memory, lowering a cache hit ratio, and prolonging an average access time of the CPU to the main memory unit.
SUMMARY OF THE INVENTION
An object of the present invention is to overcome the above-mentioned disadvantages in the prior art, and to realize a main memory control apparatus for controlling access to a main memory unit from a CPU having no snooping function and a DMA enable device, so that data access can be made to the main memory unit at a high speed while maintaining consistency of data between the cache memory and the main memory unit.
To achieve the above object, the present invention is constructed as follows.
In a main memory control apparatus for use in a computer system comprising main memory means, a CPU incorporating a cache memory, and an access enable device capable of making direct memory access to the main memory means, the main memory control apparatus controlling data access to the main memory means, the main memory control apparatus comprises a first address area allocated in a memory area of the main memory means and allowing data to be loaded into the cache memory in the CPU from the first address area but inhibiting data access from the access enable device to the first address area, and a second address area allocated in the memory area of the main memory means and allowing data access from the access enable device to the second address area but inhibiting data from being loaded into the cache memory in the CPU from the second address area, a read buffer memory permitting data stored in the main memory means to be loaded into the read buffer memory and permitting the loaded data to be read in response to a data access request from the CPU or access enable device, and a control portion making control when the CPU or access enable device issues a data access request, in such a manner as to, if data to be accessed exists in the read buffer memory, transfer the data in the read buffer memory to the CPU or access enable device issuing the access request, and if data to be accessed does not exist in the read buffer memory, read from the main memory means data at addresses different from the address under the access request from the CPU or access enable device only in lower bits of fixed length, and load the read data into the read buffer memory while transferring the read data to the CPU or access enable device issuing the access request.
With the arrangement set forth above, the data in the main memory means to which write access is made from the access enable device is always present in the second address area and will never exist in the cache memory. Therefore, consistency of data between the cache memory and the main memory means can be maintained and a need of invalidating the data in the cache memory at the time the access enable device writes data is eliminated. Also, the read buffer memory can be accessed at a higher speed than the main memory means. Accordingly, even a CPU having no snooping function that monitors access to the main memory means from other device than the CPU, i.e., the access enable device, can maintain consistency of data between the cache memory and the main memory means and shorten a data access time.
Preferably, the above main memory control apparatus further comprises a write buffer memory capable of loading therein data requested by the CPU or access enable device to be written into the main memory means, and the control portion loads data under a write request from the CPU or access enable device into the write buffer memory and writes the loaded data into the main memory means.
Also preferably, the above main memory control apparatus further comprises data error checking and correcting means, and the control portion makes control when the CPU or access enable device issues a data access request, in such a manner as to, if data to be accessed does not exist in the read buffer memory, read from the main memory means data at addresses different from the address under the access request from the CPU or access enable device only in lower bits of fixed length, instruct the data error checking and correcting means to perform error checking and correcting of the read data, and then load the read data into the read buffer memory while transferring the read data to the CPU or access enable device issuing the access request.
Data having been subjected to the error checking and correcting is loaded in the read buffer memory, and when the CPU or access enable
Hitachi , Ltd.
Kenyon & Kenyon
Nguyen Hiep T.
LandOfFree
Main memory control apparatus for use in a memory having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Main memory control apparatus for use in a memory having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Main memory control apparatus for use in a memory having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549559