Main amplifier with fast output disablement

Details Main amplifier with fast output disablement Main amplifier with fast output disablement

1997-09-17

1999-08-03

Nelms, David

Static information storage and retrieval

Read/write circuit

For complementary information

36518911, 365204, 365205, G11C 700

Patent

active

059333758

ABSTRACT:
An amplifier of a type having complementary output nodes in a data output mode of operation. When an external output enable signal is at a low level, the amplifier is enabled to output a data signal. When the output enable signal is set into a high level, the amplifier is brought into an output disable mode, in which both of its output nodes are set to a low level. The amplifier contains logic circuitry for supplying the output nodes with the data signal and output enable signal. In the output disable mode, a shunting circuit is arranged between the output nodes to provide two discharge paths for a charge stored at one of the output nodes when the signal at this output node transfers from a high level to a low level.

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