Mailbox traffic controller

Details Mailbox traffic controller Mailbox traffic controller

1996-09-11

1998-12-01

Palys, Joseph E.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711149, 711150, G06F 1202, G06F 1316

Patent

active

058451307

ABSTRACT:
A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory. Once the first processor controls access to the shared memory, the second processor knows that it must wait before attempting to control access to the shared memory. In so doing, the present invention eliminates contention between the first and second processors for control of the shared memory.

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