Mail-box design for non-blocking communication across ports of a

Details Mail-box design for non-blocking communication across ports of a Mail-box design for non-blocking communication across ports of a

1997-01-17

1998-05-12

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523005, G11C 1300

Patent

active

057516383

ABSTRACT:
A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

REFERENCES:
patent: 4435765 (1984-03-01), Uchida et al.
patent: 5293591 (1994-03-01), Dettmer
patent: 5313638 (1994-05-01), Ogle et al.
patent: 5339443 (1994-08-01), Lockwood
patent: 5349667 (1994-09-01), Kaneko
patent: 5522059 (1996-05-01), Marushima et al.
Article entitled: "QS75836 High-Speed CMOS 8K.times.36 Block-Allocated Shared-Port RAM with Flexi-Burst," Quality Semiconductor, Inc., (MDSF-00011-08) pp. 1-18 (Jan. 9,1996).

Affiliated with

Also associated with

Rating

Mail-box design for non-blocking communication across ports of a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mail-box design for non-blocking communication across ports of a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mail-box design for non-blocking communication across ports of a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-989553