Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2002-02-12
2004-01-06
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06674662
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns a digital magnetic memory cell device for reading and/or writing operations with a first and a second magnetic layer, whose magnetizations are aligned parallel or antiparallel to one another for storing digital information, whereby at least one of the magnetic layers has a magnetic anisotropy as well as a method for the reading/writing of digital information to a digital memory cell device In addition, a digital memory device comprising a multiple number of memory cell devices and a method for reading/writing digital information to such a digital memory device is disclosed.
DESCRIPTION OF THE RELATED ART
Currently, a multiple number of magnetic memories with freely selectable access (MRAM) have been developed.
An MRAM comprises a multiple number of magnetic memory cell devices. Each memory cell device comprises at least two magnetic layers, which are separated by an intermediate layer. The two magnetic layers may be magnetized parallel or antiparallel to one another. The two aforementioned states represent each time one bit of information, i.e., the logical zero (“0”) or one (“1”) state. If the relative orientation of the magnetization of the two layers is changed from parallel to antiparallel or vice versa, then the magnetoresistance typically changes by a few percent. This change in the resistance may be used for the readout from the memory cell of stored digital information. The change of cell resistance may be recognized by a voltage or current change, depending on wiring. For example, in the case of a voltage increase, the cell with a logical zero (“0”) can be validated and in the case of a voltage decrease, the cell with a logical one (“1”) can be validated.
Magnetic memory cells, which use the magnetoresistance effect for storage of digital information, have been made known from a plurality of publications.
Refer to the following in this regard:
EP 0 614,192
U.S. Pat. No. 5,343,422
EP 0 685,849
EP 0 759,619
U.S. Pat. No. 5,448,515
U.S. Pat. No. 5,276,639
U.S. Pat. No. 5,650,958
Particularly large increases in resistance in the range of several percent have been observed when the magnetization alignment changed from parallel to antiparallel and vice versa in cell structures with a giant magnetoresistance effect (GMR) or the tunnel magnetoresistance effect. Such cell structures are made known, for example, from
M. N. Balbich, J. M. Broto, A. Fert, F. Nguyen Van Dau, F. Petroff, P. Eitenne, G. Creuzet, A. Freiderich and J. Chazelas “Giant Magnetoresistance of (001)Fe/(001)Cr Magnetic Superlattices”, Physical Review Letters, Vol. 61, No. 21, p. 2472 ff. and
Teruya Shinjo, Hidefumi Yamamoto “Large Magnetoresistance of Field-Induced Giant Ferrimagnetic Multilayers”, Journal of the Physical Society of Japan, Vol. 59, No. 9, pp. 3061-3064;
WO 95/10112
WO 96/25740
EP 0 759,619 and
DE 197 17,123
An important advantage of magnetic memory cells, as described above, can be seen from the fact that the information is stored persistently in this type and manner, for example, in contrast to conventional semiconductor memories, and consequently after turning off the device in which the memory cells are used, and then again turning it on, the stored information is immediately available. In addition, storage media that are very resistant to radiation or “radiation-fast” are obtained.
A digital memory device for reading and/or writing operations has been made known from DE 195 34,856, which has a first magnetic layer and a second magnetic layer as well as a separating layer lying in between for conducting the read and/or write currents, whereby a directional change of the magnetization in one or both layers is effected, lasting over the time interval of the flowing current. The disclosure content of DE 195 34,856 with respect to a digital memory device according to the prior art is taken up to the full extent in the disclosure content of the present application.
A disadvantage of the digital memory device according to DE 195 34,856 is the fact that the addressing of the memory cell or individual memory cells of a memory cell matrix in an MRAM arrangement is conducted only by the position of the memory cell. This process is in no way optimal in regard to the time durations, particularly short or ultra-short time durations; in the case of several sequentially connected memory cells, the problem arises, in particular, that the coercive fields of the individual MRAM memory cells have a certain scatter as a result of irregularities, for example pinning centers.
As a result of this, it happens that not only is the desired memory cell addressed at the point of intersection but, rather, adjacent cells are also addressed, especially in the case of combining a plurality of the memory cell devices, which are known from DE 195 34,856, to give a memory device, e.g. in matrix form.
A magnetic memory device has become known from U.S. Pat. No. 5,448,515 that comprises a plurality of memory cells by means of which information can be a written into and read from the addressed memory cells as a result of remagnetization with the help of current pulses.
A disadvantage of this memory device was that writing in took place via currents or current pulses of unspecified time duration and the writing and reading conductors constantly enclosed an angle of 90°.
The memory device that is known from U.S. Pat. No. 5,276,639 is a superconducting magnetic memory device. In the case of this magnetic memory device, likewise, current pulses with a long duration of more than 15 ns are transformed for the purpose of writing in and reading out.
A digital magnetic memory cell device has become known from
EVERITT B A ET AL.: “SIZE DEPENDENCE OF SWITCHING THRESHOLDS FOR PSEUDO SPIN VALVE MRAM CELLS”, JOURNAL OF APPLIED PHYSICS, Vol. 81, No. 8, PART 02A, Apr. 15,1997 (1997-04-15), pages 4020-4022, XP000702728 ISSN: 0021-8979
whereby this device has a first and a second magnetic layer, an intermediate layer, two intersecting printed conductors as well as means for reversing the magnetization. The memory cell device that has become known from Everitt B. A. et al. (loc. cit.) operates via bit switching times of the order of magnitude of 1 ns. However, no data are given regarding the length of the current pulses.
BRIEF SUMMARY OF THE INVENTION
The object of the invention is to avoid the disadvantages of the prior art that are described above and, in particular, to indicate a magnetic memory cell device in the case of which the reversing process both with respect to time as well as also with respect to the selection of the respective cells, i.e., very short switching times may also be realized. In particular, a secure and rapid switching of the addressed cells will be obtained with the combination of a multiple number of memory cells or memory cell devices into one digital memory unit, for example in matrix form or in the form of an array, even if the material properties fluctuate from cell to cell within the tolerance framework.
Another aspect of the invention is the indication of a method for optimized reversing of such a memory cell device. In addition, the invention aims at minimizing the power consumption necessary for reversing and thus minimizes the heat losses discharged from a module.
The object is resolved according to the invention by the fact that in a digital magnetic memory cell device according to claim 1, the reversal means comprise devices for producing currents and/or current pulses on a first and a second printed conductor of at least two intersecting printed conductors, wherein the printed conductors intersect at a predetermined angle, so that a complete and reliable reversal of the magnetization from a parallel to an antiparallel alignment is achieved with current pulses of a time duration of <10 ns in the intersection region in the memory cell device.
If clock times of 10 ns corresponding to 100 MHz and faster are aimed at for MRAM memories, then the length of a field pulse for writing in digital information, for example, amounts to a maximum of 5 ns. Even with such
Hillebrands Burkard
Stamps Robert Leon
Ohlandt Greeley Ruggiero & Perle LLP
Phung Anh
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