Magnetoresistive memory devices and assemblies

Static information storage and retrieval – Systems using particular element – Magnetoresistive

Reexamination Certificate

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Details

C365S171000, C365S173000, C438S003000, C257S295000

Reexamination Certificate

active

06735111

ABSTRACT:

TECHNICAL FIELD
The invention pertains to magnetoresistive memory devices, such as, for example, magnetic random access memory (MRAM) devices, and also pertains to methods of storing and retrieving information.
BACKGROUND OF THE INVENTION
Numerous types of digital memories are utilized in computer system components, digital processing systems, and other applications for storing and retrieving data. MRAM is a type of digital memory in which digital bits of information comprise alternative states of magnetization of magnetic materials in memory cells. The magnetic materials can be thin ferromagnetic films. Information can be stored and retrieved from the memory devices by inductive sensing to determine a magnetization state of the devices, or by magnetoresistive sensing of the magnetization states of the memory devices. It is noted that the term “magnetoresistive device” characterizes the device and not the access device, and accordingly a magnetoresistive device can be accessed by, for example, either inductive sensing or magnetoresistive sensing methodologies.
A significant amount of research is currently being invested in magnetic digital memories, such as, for example, MRAM's, because such memories are seen to have significant potential advantages relative to the dynamic random access memory (DRAM) components and static random access memory (SRAM) components that are presently in widespread use. For instance, a problem with DRAM is that it relies on electric charge storage within capacitors. Such capacitors leak electric charge, and must be refreshed at approximately 64-128 millisecond intervals. The constant refreshing of DRAM devices can drain energy from batteries utilized to power the devices, and can lead to problems with lost data since information stored in the DRAM devices is lost when power to the devices is shut down.
SRAM devices can avoid some of the problems associated with DRAM devices, in that SRAM devices do not require constant refreshing. Further, SRAM devices are typically faster than DRAM devices. However, SRAM devices take up more semiconductor real estate than do DRAM devices. As continuing efforts are made to increase the density of memory devices, semiconductor real estate becomes increasingly valuable. Accordingly, SRAM technologies are difficult to incorporate as standard memory devices in memory arrays.
MRAM devices have the potential to alleviate the problems associated with DRAM devices and SRAM devices. Specifically, MRAM devices do not require constant refreshing, but instead store data in stable magnetic states. Further, the data stored in MRAM devices will remain within the devices even if power to the devices is shutdown or lost. Additionally, MRAM devices can potentially be formed to utilize less than or equal to the amount of semiconductor real estate associated with DRAM devices, and can accordingly potentially be more economical to incorporate into large memory arrays than are SRAM devices.
Although MRAM devices have potential to be utilized as digital memory devices, they are currently not widely utilized. Several problems associated with MRAM technologies remain to be addressed. It would be desirable to develop improved MRAM devices.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a magnetoresistive memory device. The device includes a memory bit which comprises a stack having a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line is spaced from the stack, and is configured for utilization in writing information to the memory bit.
In one aspect, the invention encompasses a magnetoresistive memory device assembly. The assembly includes an array of individual magnetoresistive memory devices. The devices include memory bits. The individual memory bits comprise a stack of a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is proximate the stack and utilized for reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line and is configured for utilization in writing information to the memory bit. The first conductive line extends across a first set of several of the individual magnetoresistive memory devices of the array, and the second conductive line also extends across the first set of the individual magnetoresistive memory devices of the array. A first transistor is electrically connected with the first conductive line and accordingly electrically connected with the first set of individual magnetoresistive memory devices. Additionally, a second transistor is electrically connected with the second conductive line, and accordingly electrically connected with the first set of the individual magnetoresistive memory devices of the array.
In one aspect, the invention encompasses a method of storing and retrieving information. A magnetoresistive memory device is provided. The device comprises a memory stack having a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is provided proximate the stack and utilized for reading information from the memory bit, and a second conductive line is spaced from the stack by a greater distance than the first conductive line and utilized for writing information to the memory bit. The first conductive line is operated at a maximum amperage of from about 500 nanoamps to about 1 microamp during reading of information from the memory bit, and the second conductive line is operated at a maximum amperage of from about 1 milliamp to about 10 milliamps during writing of information to the memory bit.


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patent: 1 085 586 (2001-03-01), None
patent: 1 143 537 (2001-10-01), None
patent: PCT US 03/ 00120 (2003-01-01), None

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