Magnetoresistive memory device

Details Magnetoresistive memory device Magnetoresistive memory device

2001-11-05

2003-09-23

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S196000

Reexamination Certificate

active

06625057

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2000-351787, filed on Nov. 17, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory integrated circuit (IC) devices configured using memory cells of the current readout type.
2. Description of Related Art
Currently available memory cells adaptable for use in semiconductor memory IC devices include those cells of the type performing data storage depending upon whether a current flowing during cell selection is present or absent or alternatively whether such current is large or small in amount. This type of memory cells will be referred to hereinafter as the “current-driven” type memory cells in the description. Known current-driven memory cells include non-volatile memory cells suitable for use with electrically programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM) chips, which cells are of the multilayered gate type metal oxide semiconductor (MOS) transistor structure having a floating gate or alternatively the metal nitride oxide semiconductor (MNOS) transistor structure, the metal oxide nitride oxide semiconductor(MONOS) transistor.
Other known memory cells include magnetic random access memory (MRAM) cells employing magnetoresistance (MR) effects, thyristor-RAM (T-RAM) cells using negative differentiation resistance each formed of a thyristor and a select transistor (such as disclosed in F. Nemati and J. D. Plummer, 1996 Symp. on VLSI Tech. at pp. 66-77, as will be referred to as “Document #1” or simply “D1” in the rest of the description), tunnel switch diode (TSD) cells using TSDs (as recited for example in H. J. Levy et al., IEEE Journal of Solid-State Circuits, vol. 33, April 1998, pp. 669-672, to be referred to as “Document #2” or “D2” hereafter), and a specific type of dynamic random access memory (DRAM) cells called “gain cells” among those skilled in the semiconductor memory art. The gain-cell type DRAM cells are generally categorized into the two: the one that stores a packet of electrical charge carriers while using the gate of a sensing MOS transistor as its storage node, and the other that is designed to utilize the so-called “backgate bias” effect for storage of electrical charge with the bulk region (channel body) of a sense MOS transistor being used as the storage node thereof.
In the case of memory cells of the floating gate type for general use in EPROMs and EEPROMS, data determination or “judgment” is done by detection of a difference of drain current in view of the fact that the threshold voltage is different depending upon the amount of electrical charge being presently accumulated at the floating gate of interest. It should be required at this time that a drain voltage be suppressed at a low potential level for preclusion of unwanted occurrence of writing during reading. Typical examples of prior known sense amplifier circuitry used in EEPROMs are shown in
FIGS. 55 and 56
.
The sense amplifier system shown in
FIG. 55
is the one as taught by N.Ohtsuka et al., “A 62 ns 16 Mb CMOS EPROM with Address Transition Detection Technique,” ISSCC Digest of Technical Papers, February 1991, pp. 262-263. The sense amp system of
FIG. 56
is disclosed in G. Canepa et al., “A 90 ns 4 Mb CMOS EPROM,” ISSCC Digest of Technical Papers, February 1988, pp. 120-121. Note here that the both circuits are shown so that portions less relevant to this invention are eliminated from the illustrations.
The sense amp circuits of
FIGS. 55-56
are both designed to perform an operation for establishment of a specific bitline voltage potential as determinable by load-to-memory cell ratios in turn-on resistance values thereof, also known as “ratio” operation among those skilled in the art to which the invention pertains; thus, a bitline potential changes from 0.5 V to 1V or more or less in a way pursuant to the threshold voltage level of a memory cell. Electrons are accumulated at the cell's floating gate, causing a bit line associated with a memory cell of higher threshold voltage (and thus the cell's drain) to potentially go high. The remaining, non-selected memory cells are such that their word line-coupled control gates are kept at 0V; thus, if the drain potential is high then electrons are readily injectable thereinto. The presence of this high drain potential can cause writing errors, especially for those memory cells presently in an erase state (ordinarily, logic data “1” storage state).
In the case of multiple-value data storage, a four-value storage scheme based on a threshold value distribution shown for example in
FIG. 35
is representatively known, which is found in M.Bauer et al., ISSCC95 at pp. 132-133. One typical sense amplifier circuitry suitable for use in the case of such multi-value storage is configured as shown for example in
FIG. 56
, which is suggested from M.Bauer et al., “A Multilevel-Cell 32 Mb Flash Memory,” ISSCC Digest of Technical Papers, February 1995, pp. 132-133. Here also, any part irrelevant to this invention is eliminated from the illustration.
As in the case of two-value storage, the sense amp circuit shown in
FIG. 56
is designed to do the “load-to-cell turn-on ratio” operation discussed above. Accordingly, in accordance with a present threshold voltage of a memory cell, its associated bit line potentially increases from 0.5V and then goes beyond 1V. In addition, the required sense time period is longer than that of the two-value storage due to the fact that upper and lower level data bits are read out sequentially-that is, the upper level data bit is first read and thereafter the lower bit is read out. Even when word-line closing control is done after completion of each bit data reading, possible stress becomes stronger when compared to the two-value case, resulting in the circuitry suffering from high risks of writing errors.
MRAM cells also include memory cells of the type utilizing magnetic tunnel junction (MTJ) architectures, called “MTJ-MRAM” cells, examples of which are disclosed in R.Scheuerlein et al., 2000 ISSCC at pp. 128-129 (“Document #3” or “D3”) and M.Durlam et al., 2000 ISSCC, pp. 130-131 (“D4”). These MTJ-MRAM cells taught thereby utilize the fact that electrical resistance when spins of ferromagnetic materials with an interposed tunneling dielectric film forming an MTJ are parallel in direction is different in value that when the spins are anti-parallel (the resistance is large when spins are antiparallel). With such MTJ-MRAM cells, a resistance difference becomes smaller with an increase in voltage to be applied to the MTJ; thus, it is required that any application voltage be suppressed in potential. Although the resistance difference gets larger owing to research and development results in recent years, the application voltage is strictly required to fall within a limited range of from 0.2 to 0.4V; otherwise, the resistance different would decrease thereby making the data judgment more difficult.
A basic structure of MTJ-MRAM cell is shown in
FIG. 33A
, and equivalent circuitry of it is depicted in FIG.
33
B. Also see
FIG. 34
, which shows a relation of the MTJ-MRAM cell's resistance change versus a bias voltage used, sometimes called the “bias voltage-dependent resistance change characteristic,” as taught by M.Durlam et al., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements,” ISSCC 2000 slide supplement, February 2000, pp. 410-411. As shown in
FIG. 33A
, the MTJ-MRAM cell is designed so that its MTJ is formed of ferromagnetic films
331
,
333
with a tunnel dielectric film
332
sandwiched therebetween. The lower ferromagnetic film
331
is spin-fixed whereas the upper film
333
is spin-variable. The upper ferromagnetic film
333
's spin drive is done by use of a bit line BL and a write-use word line W-WL, which lines run at right angles to each other with the MTJ

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