Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-27
2003-10-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000, C257S421000
Reexamination Certificate
active
06630703
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a memory cell configuration having a magnetoresistive memory element, and to a method for producing a memory cell configuration having a magnetoresistive memory element.
In the prior art, the expression magnetoresistive element means a structure which has at least two ferromagnetic layers and a non-magnetic layer disposed in between them. Depending on the construction of the layer structure, a distinction is in this case drawn between a GMR element, a TMR element and a CMR element (see S. Mengel, Technologieanalyse Magnetismus, Band 2, XMR-Technologien, Herausgeber VDI Technologiezentrum Physikalische Technologien [Technological analysis of magnetism, Volume 2, XMR technologies, issued by VDI Technology Center for Physical Technologies], August 1997).
The term GMR element is used for layer structures which have at least two ferromagnetic layers and a non-magnetic, conductive layer disposed in between them and which have what is referred to as a GMR (giant magnetoresistive) effect. The expression GMR effect refers to the fact that the electrical resistance of the GMR element is dependent on whether the magnetization directions in the two ferromagnetic layers are aligned parallel in the same direction or in opposite directions. In comparison to what is referred to as the AMR (anisotropic magnetoresistive) effect, the GMR effect is large. The AMR effect refers to the fact that the resistance in magnetic conductors differs parallel to and at right angles to the magnetization direction. The AMR effect is a volume effect which occurs in single ferromagnetic layers.
In the prior art, the term TMR element is used for tunneling magnetoresistive layer structures, which have at least two ferromagnetic layers and an insulating, non-magnetic layer disposed in between them. The insulating layer is in this case sufficiently thin to allow a tunneling current to flow between the two ferromagnetic layers. These layer structures likewise have a magnetoresistive effect, which is produced by a spin-polarized tunneling current through the insulating, non-magnetic layer disposed between the two ferromagnetic layers. In this case as well, the electrical resistance of the TMR element is dependent on whether the magnetization directions in the two ferromagnetic layers are disposed parallel in the same direction or in opposite directions. The relative resistance change is in this case from approximately 6% to approximately 40%.
A further magnetoresistive effect, which is referred to as the colossal magnetoresistive effect (CMR effect) owing to its magnitude (relative resistance change of 100 to 400% at room temperature) requires a strong magnetic field to switch between the magnetization states, owing to its high coercivity forces.
It has been proposed (see, for example, D. D. Tang et al., IEDM 95, pages 997 to 999, J. M. Daughton, Thin Solid Films, Volume 216 (1992), pages 162 to 168, Z. Wang et al, Journal of Magnetism and Magnetic Materials, Vol. 155 (1996), pages 161 to 163) for GRM elements to be used as memory elements in a memory cell configuration. The memory elements are connected in series via read lines. Word lines run transversely with respect to these read lines and are insulated both from the read lines and from the memory elements. Signals applied to the word lines result in a current flowing in the word line which produces a magnetic field, which influences the memory elements located underneath it, if its intensity is sufficient. Information written using x/y lines, which cross at the memory cell to be written to. Signals are applied to them and cause a magnetic field, which is sufficient for remagnetization, at the crossing point. In the process, the magnetization direction in one of the two ferromagnetic layers is switched. The magnetization direction in the other of the two ferromagnetic layers remains unchanged, however. The fixing of the magnetization direction in the last-mentioned ferromagnetic layer is achieved by using an adjacent antiferromagnetic layer, which fixes the magnetization direction, or by the switching threshold for this ferromagnetic layer being increased by using a different material or different dimensions, for example by increasing the layer thickness in comparison to that of the first-mentioned ferromagnetic layer.
Annular memory elements which are based on the GMR effect have been proposed in U.S. Pat. No. 5,541,868 and U.S. Pat. No. 5,477,483. A memory element including a stack which has at least two annular ferromagnetic layer elements and a nonmagnetic conductive layer element which is disposed between them, and which is connected between two lines. The ferromagnetic layer elements have different material compositions. One of the ferromagnetic layer elements is magnetically hard, and the other is magnetically softer. In order to write information, the magnetization direction in the magnetically softer layer element is switched, while the magnetization direction in the magnetically harder layer element remains unchanged.
With regard to the question as to whether memory cell configurations having magnetoresistive memory elements will become technologically important, one significant factor, among others, is whether such memory cell configurations can be produced using a semiconductor process technique. Neither this problem nor possible solutions have so far been described in the literature.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration and a method for its production which overcome the hereinafore-mentioned disadvantages of the heretofore-known memory cell configurations and their methods of production of this general type.
The present invention concerns specifying a memory cell configuration having magnetoresistive memory elements which can be produced using a semiconductor process technique, and a method for producing a memory cell configuration having magnetoresistive memory elements using a semiconductor process technique.
This problem is solved by a memory cell configuration having a cell array which has first lines, second lines, and a peripheral area and is disposed in the form of a grid in a first plane; first magnetoresistive memory elements in the cell array disposed between the first lines and the second lines for addressing said magnetoresistive memory elements; at least one first metalization plane, one second metalization plane and contacts in the peripheral area of the cell array, the contacts providing local electrical connections between the first metalization plane and the second metalization plane. The first lines and the first metalization plane are in the same plane for making contact with one another, and the second lines and the contacts are disposed in the same plane.
In one embodiment of the memory cell configuration an intermetal dielectric surrounds the second lines and contacts.
In another embodiment of the memory cell configuration the first lines and the first metalization plane have substantially the same thickness.
In another embodiment of the memory cell configuration the third lines in the cell array and the second metalization plane are in the same plane, and second magnetoresistive memory elements are disposed in a second plane between the second lines and the third lines.
In another embodiment of the memory cell configuration the third lines and the second metalization plane have essentially the same thickness.
In another embodiment of the memory cell configuration the magnetoresistive memory element has a first ferromagnetic layer, a non-magnetic layer and a second ferromagnetic layer, the first ferromagnetic layer and the second ferromagnetic layer contain one of Fe, Ni, Co, Cr, Mn, Gd and Dy and each have a thickness in a range between 2 nm and 20 nm, and the non-magnetic layer contains Al
2
O
3
, NiO, HfO
2
, TiO
2
, NbO, SiO2, Cu, Au, Ag or Al and has a thickness of between 1 nm and 5 nm.
In another embodiment of the memory cell configuration there is a diffusio
Scheler Ulrich
Schwarzl Siegfried
Greenberg Laurence A.
Ho Tu-Tu
Infineon - Technologies AG
Locher Ralph E.
Nelms David
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