Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-09-04
2002-11-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S173000
Reexamination Certificate
active
06487109
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a magnetoresistive memory and a method of reading memory cells in such a magnetoresistive memory.
Magnetoresistive memories represent an alternative to conventional DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories) and non-volatile memories such as flash memories or EEPROM (Electrically Erasable Programmable Read Only Memory). They are formed of a configuration of memory cells to which bit lines and word lines are linked. The individual memory cells of a magnetoresistive memory are formed of two magnetic elements separated by a dielectric. One of the magnetic elements is hard-magnetic and therefore has a fixed direction of flux, whereas the other is soft-magnetic, and its orientation can be reversed by applying appropriate switching currents to the bit lines and word lines. The dielectric between the two magnetic elements is known as a tunnel dielectric, for instance a layer with a thickness of 2 nm, which is suitable as a tunnel dielectric. The specific feature of a tunnel dielectric is that its resistance depends on the magnetic field surrounding it. When the two magnetic elements on either side of the tunnel dielectric are oriented in the same direction, the dielectric has a different resistance value than when the magnetic flux directions of the two magnetic elements are the inverse of one another. By applying a suitable voltage to the bit lines and word lines, the instantaneous value of the resistance in the tunnel dielectric can be determined, and thus the orientation of the magnetic elements can be deduced. Thus, an overall binary state system is produced, which is suitable for storing digital information.
In such a configuration of memory cells, it is possible to provide parallel bit lines and word lines over and under the actual memory cells, that are in turn provided at a right angle to each other. At the margin of the memory cell configuration, the bit lines and word lines can then be carried over into additional circuits for writing and reading.
Arrays of MRAM (Magnetoresistive Random Access Memory) mass memories have not yet been presented as products. only smaller configurations (arrays) are available, which are usually based on the “current in-plane” principle, whereas the “current perpendicular to plane” principle holds better prospects for mass memory applications.
Magnetoresistive memories offer particular fundamental advantages, such as simple production, non-volatile data maintenance, and good shrink suitability. Their suitability as mass memories is largely dependent upon whether sufficiently large memory cell blocks can be realized. Arrays of competitive mass memories must simultaneously satisfy the following requirements:
1. The array must allow a size of several hundred by several hundred memory cells.
2. The read signal must have a definite minimum size in order to make possible a sufficiently reliable evaluation.
Examples of Semiconductor Products:
DRAMs require approx. 100-150 mV. They perform voltage evaluation at the array margin using read amplifiers, which sit in the pitch.
Flash memories (embedded) require approx. 10 &mgr;A. They carry out current evaluation with read amplifiers in the periphery. SRAMs work with on-currents of 150 &mgr;A and negligible off-currents. They achieve array access times of from 600 ps to 1.2 ns.
Precise values cannot be given in advance for an MRAM; rather, it must be checked on a case-by-case basis whether the read signal is sufficient for a reliable evaluation, which is insensitive to noise. In any case, read amplifiers are not needed in the pitch. This relaxes the requirements.
3. The energy consumption in the read operation should be comparable to that of a DRAM or lower (1 pJ to 1 nJ, depending on the architecture).
These requirements also apply to a mass memory application of MRAMs.
In the prior art, various suggestions have been made for configuring magnetoresistive memory cell configurations. But the amplifier circuits put forward there tend to exhibit stability problems in practice.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a magnetoresistive memory and a method of reading or operating a magnetoresistive memory which overcome the above-mentioned disadvantages of the heretofore-known methods and devices of this general type and which allows a suitable architecture for reliably writing, reading, and erasing magnetoresistive memory cells in arrays of such cells, i.e. in magnetoresistive memories.
With the foregoing and other objects in view there is provided, in accordance with the invention, a magnetoresistive memory, including:
magnetoresistive memory cells having respective first poles and second poles and being disposed in an array formed by rows and columns;
bit lines assigned to the columns, the bit lines being connected to the first poles of the magnetoresistive memory cells disposed in associated ones of the columns, the bit lines having first ends and second ends;
word lines assigned to the rows, the word lines being connected to the second poles of the magnetoresistive memory cells disposed in associated ones of the rows, the word lines having first ends and second ends;
a read voltage source;
first switching elements connected such that the read voltage source is separately connectable to the first ends of the word lines via the first switching elements;
an evaluation line;
second switching elements;
a voltage evaluator having at least one input, the at least one input being separately connectable, via the evaluation line, to the first ends of the bit lines by the second switching elements;
a first terminating resistor branching from the evaluation line;
third switching elements; and
an impedance converter having an input connected to the evaluation line and having an output separately connectable to the second ends of the bit lines and the word lines with the third switching elements.
The invention is based on the idea of generating a voltage which is dependent on the resistance of a memory cell that is being read, and making this voltage so loadable through the use of an impedance converter that the word lines and bit lines can be sufficiently held at a stable voltage level.
In other words, the invention is thus first aimed at a magnetoresistive memory which includes: a configuration of magnetoresistive memory cells in several rows and/or several columns; a bit line for each of the columns, which is connected to first poles of the memory cells belonging to the column; a word line for each of the rows, which is connected to second poles of memory cells belonging to the row; a read voltage source, which is separately connectable to first ends of the word lines by switching elements; a voltage evaluator, whose at least one input is separately connectable to first ends of the bit lines by switching elements, by way of an evaluation line; whereby a first terminating resistor branches from the evaluation line. The inventive magnetoresistive memory is characterized by an impedance converter, whose input is connected to the evaluation line and whose output is separately connectable the second ends of the bit lines and word lines by switching elements.
The plurality of memory cells, which are organized in an array includes rows and columns. Because, in order to execute the inventive method, and thus in order to inventively utilize the impedance converter, a voltage is applied to word lines and bit lines which are not connected to the memory cell that is being read, it is necessary to provide more than one line at least in one of the two given dimensions, i.e. in rows or columns. Two is thus the minimum number of memory cells with which it is practical to apply the invention. Of course, a higher number of memory cells is desirable, which will typically be given in practice.
The read voltage source, which is connectable to the word lines, is in the position to supply a sufficient voltage to the active word line(s) to allow evaluation of the voltage still present at
Berg Hugo Van Den
Thewes Roland
Weber Werner
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Hien
LandOfFree
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