Magnetoelectronic memory array

Details Magnetoelectronic memory array Magnetoelectronic memory array

2000-03-22

2001-10-23

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Hall effect

C365S009000

Reexamination Certificate

active

06307774

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to magneto-electronic devices which can be used for a variety of applications, including as memory elements in a random access memory array. In particular, the present invention is directed to a hybrid Hall Effect device which includes a ferromagnetic material magnetically coupled to a conventional Hall Effect plate. The hybrid device can be coupled directly to a bias source and combined with other semiconductor structures, such as transistor isolation elements. The resulting array architectures have improved cross-talk, signal level and signal-to-noise performance characteristics.
BACKGROUND OF THE INVENTION
Hybrid Hall Effect devices are described in my earlier application (4) above. The present invention is directed to specific embodiments of such devices, as well as preferred arrangements of the same which result in improved memory elements and performance of memory arrays.
By modifying a classic Hall plate, and in particular by coupling it to a ferromagnetic material, novel hybrid devices can be created that are useful for applications in high density nonvolatile memory and logic gate environments. A schematic figure that can be used to represent the novel Hybrid Hall Effect Device
10
is illustrated in
FIG. 1. A
standard representation for a classic four-terminal Hall plate
12
is a cross centered in a square. Two opposing terminals are used for current bias (or voltage bias), for example terminals
14
and
16
, and the other two terminals
18
and
20
are used for sensing a bipolar Hall voltage.
One embodiment of the hybrid Hall Effect device described in my earlier application (4) incorporates a ferromagnetic film F
22
fabricated to be electrically isolated from the Hall plate but covering a portion of the area of the Hall plate such that an edge
26
of the film is over a central region of the plate. Local, fringe magnetic fields from the edge of the ferromagnetic film are perpendicular to the plane of the plate, may point “up” or “down” depending on the orientation of the magnetization in F, and have an average value B
av
in the active region of the device. For constant bias current the sensed Hall voltage has opposite polarity when the fringe fields are “up” compared with when they are “down.” The magnetization
M
24
of F is typically in the plane of F and lies along an axis parallel with that of the bias current. Other orientations can be used however, such as magnetizations that are perpendicular to the plane instead. The magnetization can be configured to have two stable states along this axis, with the two states corresponding to “up” or “down” fringe fields near the edge of F, positive or negative Hall voltage, and thus representing a binary bit of information “1” or “0”. The magnetization state can be set (written) to be positive or negative by using the magnetic field associated with a positive or negative current pulse transmitted down an integrated write wire that is contiguous with F, discussed in detail in application (4) above, as well as below. It follows that such a device can be used as the nonvolatile storage element in an array of elements comprising a nonvolatile random access memory (NRAM).
FIG. 1
depicts the first embodiment of the Hybrid Hall Effect device, generally referred to hereafter as a “modified hall plate.” Again, while application (4) describes one preferred physical embodiment of the modified hall plate, it will be understood by those skilled in the art that a variety of layer materials, layer structures and layer arrangements are possible.
My earlier application (4) described various arrangements of the type of hybrid Hall Effect devices described above which could be used as a memory array. In particular, a linear row of elements can be constructed with such devices, so that the positive current bias terminal of one element (e.g. terminal
14
in
FIG. 1
) is connected in series with the negative current bias terminal of another (e.g. terminal
16
). In this way, a number n
i
of elements is combined in one row and biased by a single current (or voltage) supply source, I
B
or V
B
. Each element of that row can then be sensed by a unique sense amplifier devoted to that element. Alternatively, a single amplifier can be used for all elements in the row if a selection and isolation device is used to isolate each element from all of the other elements. A field effect transistor (FET) used in this manner can be referred to as a “select transistor.”
While the above memory array arrangement is satisfactory for many environments, other applications may experience undesirable problems when a number n
j
of rows are fabricated together to form an array of this type. In particular, because the hybrid Hall Effect memory cells are not isolated from each other, Hall voltages generated at one cell can dissipate through common connections to neighbor cells and the signal level, as well as the signal to noise ratio (SNR) of the readout voltage for every cell can be degraded. There is a need, therefore, for hybrid Hall Effect memory cell embodiments and arrangements which eliminate and/or reduce such performance problems.
SUMMARY OF THE INVENTION
An object of the present invention therefore is to provide an improved architecture for a hybrid Hall Effect device to be used as a memory cell in a memory array.
A further object of the present invention is to provide an improved architecture for a random access memory array of hybrid Hall Effect memory cells which permits a bias voltage (or current) to be provided to each such cell, thus resulting in improved signal level and signal-to-noise ratio characteristics for such array.
Another object of the present invention is to provide an improved memory cell for application in a memory array environment, which affords improved cell isolation and reduced cross talk between cells in the array.
According to the present invention, an array of modified Hall Effect plate memory elements with improved performance is formed by providing the bias source I
B
or (V
B
) directly to each cell in the array to increase the SNR. The outputs of the Hall Effect plate memory elements can be coupled to a select transistor which acts as an isolation element to reduce cross-talk between cells in the array. In this way, the magnetization state of the ferromagnetic layer and the output of the Hall Effect plate for each hybrid memory cell is retained and isolated from other hybrid memory cells.
The bias source and ground for the cells are provided by additional individual levels of lithography, and this choice increases the number of fabrication steps (and levels) by comparison with the simpler array described earlier. However, the hybrid Hall Effect device requires far fewer levels than conventional dynamic random access memories (DRAM) and this economy of fabrication is only marginally diminished by the addition of a few levels.
In the preferred cell architecture, one selection transistor is fabricated within each cell. When a select transistor for a particular cell is addressed the Hall voltage developed by that cell is the only voltage transmitted to the input line of a sense amplifier that is common to a column of cells. The signal to noise ratio (SNR) can be adjusted to any desired value and there is minimal (or zero) signal leakage between neighboring cells.
Thus, the preferred cell architecture is comprised of a single modified hall plate and an accompanying single select FET that can be fabricated with a small cell area and a high packing density. Furthermore, in another embodiment of the invention, if readout voltages are sufficiently large as to accommodate some dissipation as the voltage is transmitted across the FET, then select transistors with relatively poor operating parameters, or other high impedance elements such as resistors or diodes can be used. Such transistors and high impedance elements can be made by thin film processing, and this would permit the fabrication of multiple layers of cells, further increasing density.
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