Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-14
2004-10-12
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C438S003000
Reexamination Certificate
active
06803615
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to data storage and more particularly to an improved structure for a conductive line connected to a Magnetic Tunnel Junction (MTJ) of a Magnetic Random Access Memory (MRAM) cell.
2. Description of the Prior Art
A wide range of presently available media for data storage vary in several attributes including access speed, duration of reliable storage, and cost. Static Random Access Memory (SRAM) is the storage medium with the best access speed for the cost in applications such as cache memories. However, SRAM is volatile, meaning that it only maintains storage while power is continuously applied. Accordingly, computer users endure lengthy waits when they power-up their computers while substantial amounts of data are written from non-volatile but slow media, such as magnetic disks, into much faster random access memory (e.g., SRAM).
Flash memory is a solid-state storage medium that provides moderate access times and that is non-volatile. Flash memory has the disadvantage that it has a limited lifetime, on the order of one million cycles per cell, after which a cell can no longer be written to. This lifetime is orders of magnitude too short for a random access memory in most modern computing system.
Another solid-state storage medium is Magnetic Random Access Memory (MRAM), which employs a Magnetic Tunnel Junction (MTJ) formed of layers of magnetic material and an insulating barrier.
FIG. 1
shows a cross-section of a prior art MRAM cell
10
including an MTJ
12
formed of a pinned layer
14
and a free layer
16
, which are magnetic layers typically formed of ferromagnetic materials, and a thin dielectric layer
18
disposed between layers
14
and
16
. Pinned layer
14
has a magnetic moment orientation
20
that is fixed from rotating, while free layer
16
has a magnetic moment orientation
22
that is free to rotate in response to applied magnetic fields. Methods of pinning a pinned layer
14
are well known in the art and include the use of an adjacent antiferromagnetic layer
24
.
In an MRAM unit
10
, a bit of data is encoded in the direction of the magnetic moment orientation
22
of the free layer
16
relative to the magnetic moment orientation
20
of the pinned layer
14
. As is well known in the art, when the two magnetic moment orientations
20
and
22
are parallel the resistance measured across the MTJ
12
is relatively low, and when the two magnetic moment orientations
20
and
22
are antiparallel the resistance measured across the MTJ
12
is relatively high. Accordingly, one can determine whether the magnetic moment orientations
20
and
22
are parallel or antiparallel by reading the resistance across the MTJ
12
with a read current. Typical read currents are on the order of 1-50 &mgr;A.
In an MRAM unit
10
, the state of the bit, parallel or antiparallel, is varied by applying a write current I
W
, typically on the order of 1-25 mA, through two conductors, a bit line
28
and a digit line
26
, situated proximate to the MTJ
12
. The bit line
28
and the digit line
26
cross one another at approximately right angles above and below the MTJ
12
. As is well known in the art, although the pinned layer
14
is depicted in
FIG. 1
as nearer to the bit line
26
, an MRAM cell
10
also functions with the pinned layer
14
nearer to the digit line
28
.
As is well known, a magnetic field develops around an electric current in a wire. Accordingly, two magnetic fields arise when write currents I
W
are simultaneously applied to both the bit line
28
and the digit line
26
. The two magnetic fields combine at the free layer
16
to influence the magnetic moment orientation
22
. The magnetic moment orientation
22
of the free layer
16
is changed between the parallel and antiparallel states by changing the direction of the write current
1
W
in either the bit line
28
or the digit line
26
. Changing (by a write control circuit, not shown) the direction of the write current I
W
in one of the lines
26
or
28
reverses the direction of the magnetic field around that conductor and thereby reverses the direction of the combined magnetic field at the free layer
16
.
In an MRAM unit
10
, the state of the bit is read by passing a read current I
R
through the MTJ
12
. The bit line
28
is used to conduct the read current I
R
to the MTJ
12
. In some embodiments a transistor (not shown) is used to allow the read current I
R
to flow from the bit line
28
through the MTJ
12
and out through a bottom lead
25
during a read operation while preventing the write current I
W
from flowing through the MTJ
12
during a write operation. An insulating spacer
27
is disposed between the bottom lead
25
and the digit line
26
to prevent shorting between the two.
FIG. 2
shows a cross-section of an array
30
of MRAM cells
10
of the prior art. A line
1
—
1
shows the orientation of the cross-section shown previously in FIG.
1
.
FIG. 2
illustrates three MRAM cells
10
connected to one bit line
28
. An array
30
can include any number of MRAM cells
10
on a single bit line
28
. Similarly, there can also be any number of MRAM cells
10
associated with each digit line
26
arranged in a line extending perpendicularly to the plane of the drawing. Accordingly, an array
30
typically consists of a lattice of digit lines
26
and bit lines
28
, with an MRAM cell
10
at each point of intersection between the bit lines
28
and the digit lines
26
. In order to affect a particular MRAM cell
10
, control circuitry (not shown) is used to select the appropriate bit line
28
and digit line
26
. For a write operation to the selected MRAM cell
10
, the control circuitry directs a write current through each of the appropriate bit and digit lines
28
and
26
. A transistor
32
, which may be a CMOS transistor, is connected by a conductive line
34
to the MTJ
12
to selectively isolate the MTJ
12
from the remainder of the circuitry. During a write operation, the transistor
32
is open to prevent the write current I
W
in the bit line
28
from flowing through the MTJ
12
. During a read operation, however, the state of the transistor
32
is switched to closed so that the read current can flow through the MTJ
12
.
Referring again to
FIG. 1
, the magnetic moment orientation
22
of the free layer
16
is represented as a single vector with a unique direction. While the direction of the magnetic moment within the free layer
16
generally has the orientation
22
, near the edges of the free layer
16
the magnetic spins tend to curl away from the orientation
22
due to a demagnetization field. As noted above, when the two magnetic moment orientations
20
and
22
are parallel the resistance measured across the MTJ
12
is relatively low, and when the two magnetic moment orientations
20
and
22
are antiparallel the resistance measured across the MTJ
12
is relatively high. However, the curling effect tends to decrease the relatively high resistance and to increase the relatively low resistance such that the difference between the two states is reduced. Further, the curling effect is a dynamic effect and varies over time, causing the resistance across the MTJ
12
to continually vary in either the high or low resistance states. Thus, the reproducibility of the signal amplitude, the voltage measured across the MTJ
12
, is reduced by the curling effect. The curling effect and its influence on reproducibility are also exacerbated by high temperatures and stray magnetic fields, making the MRAM cell
10
less stable and more likely to switch states unintentionally.
U.S. Pat. No. 6,174,737 B1 issued to Durlam et al., discloses an MRAM having a bit line, a magnetic memory element, and an electrically conductive layer disposed between the bit line and the magnetic memory element. Durlam et al. also discloses a Permalloy field focusing layer used in conjunction with both bit and digit lines. Durlam et al. does not explain specifically how a field focusing layer functions, except t
Hiner Hugh Craig
Shi Xizeng
Sin Kyusik
Carr & Ferrell LLP
Elms Richard
Western Digital (Fremont) Inc.
Wilson Christian D.
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