Magnetic random access memory with reduced parasitic currents

Details Magnetic random access memory with reduced parasitic currents Magnetic random access memory with reduced parasitic currents

2002-05-15

2004-11-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

06826077

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to data storage devices. More specifically, the invention relates to magnetic random access memory (MRAM) with reduced parasitic currents.
DESCRIPTION OF THE RELATED ART
Magnetic random access memory (MRAM) is a non-volatile memory that is being considered for long term data storage. Performing read and write operations in MRAM devices would be orders of magnitude faster than performing read and write operations in conventional long term storage devices such as hard drives. In addition, the MRAM devices would be more compact and would consume less power than hard drives and other conventional long term storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line. The memory cell stores a bit of information as an orientation of a magnetization. The magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of ‘0’ and ‘1.’
The magnetization orientation affects the resistance of a memory cell such as a spin dependent tunneling junction device. For instance, resistance of a memory cell is a first value R if the magnetization orientation is parallel, and the resistance of the memory cell is increased to a second value R+&Dgr;R if the magnetization orientation is changed from parallel to anti-parallel. The magnetization orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance state of the selected memory cell.
Sensing the resistance state of a single memory cell in the array can be unreliable. All memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns (the array of memory cells may be characterized as a cross point resistor network).
Moreover, if the memory cell being sensed has a different resistance state due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to parasitic or “sneak path” currents. The parasitic currents can interfere with the sensing of the resistance states. Therefore, there is a need for systems and methods that address these and/or other problems associated with MRAM devices of the prior art.
SUMMARY OF THE INVENTION
The present invention provides systems and methods for storing data. In one embodiment of the invention, a magnetic random access memory (MRAM) cell includes a magnetic tunnel junction and a non-magnetic tunnel junction (NMTJ). In another embodiment, an MRAM device includes a first wire for carrying a current for reading a bit value stored in an MRAM cell, a second wire for carrying a current for reading a bit value stored in the MRAM cell, a first magnetic layer located between the first wire and the second wire, a second magnetic layer located between the first wire and the second wire, a first insulating layer that is located between the first magnetic layer and the second magnetic layer, and a second insulating layer that is located between the second magnetic layer and the second wire.
In yet another embodiment, a method for reading a value stored in a magnetic random access memory (MRAM) cell includes providing a voltage differential across a magnetic tunnel junction of the memory cell and providing a voltage differential across a non-magnetic tunnel junction (NMTJ) of the memory cell.


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