Magnetic random access memory with memory cells of different...

Details Magnetic random access memory with memory cells of different... Magnetic random access memory with memory cells of different...

2003-04-24

2004-06-29

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S173000, C365S171000, C365S189090

Reexamination Certificate

active

06757189

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high density magnetic random access memory (MRAM), and more specifically, to an MRAM comprising magnetic tunnel junction (MTJ) cells with different resistance characteristics and a transistor connected in parallel or in series with the MTJ cells, so as to be a control element for reading data without complicated reading procedure and timing, resulting in high density package of magnetic random access memory.
2. Description of the Prior Art
The MRAM has advantages such as non-volatility, high integrity, high access speed and strong radiation resistance. When reading the memory data, a voltage source is provided in a selected MTJ cell, so as to determine the digit value of the data by reading the sensing current. However, when writing the memory data, the conventional method employs two current lines (namely, a bit line and a write word line) to select a MRAM by inducing a magnetic field, so as to change the magnetization orientation of the magnetic material and update the data state.
It is known that the MRAM between the bit line and the write word line is a stacked structure formed of multi-layered magnetic materials. Basically, the MRAM comprises a soft magnetic layer, a nonmagnetic conductor or a tunnel barrier, and a hard magnetic layer. By the magnetization orientations of the two magnetic layers, which are in parallel in the same direction or in opposite directions, the data state is determined to be “1” or “0”. In the prior arts, such as U.S. Pat. No. 6,418,046 entitled “MRAM structure and system” filed by Naji and Peter K. (Gilbert, Ariz.) and “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects”, VLSI 2002 by M. Durlam et al., the MRAMs are composed of a MTJ cell and a transistor. Two adjacent transistors share the same source and isolation region such that the memory cell size formed thereof is 20 F
2
(wherein F is the characteristic size of technology node). However, compared with the dynamic random access memory (DRAM), such as an example described in “A Highly Manufacturable 110 nm DRAM Technology with 8 F
2
Vertical Transistor Cell for 1 Gb and Beyond”, VLSI 2002 by H. Akatzu et al., the size of the MRAM is more than two times of 8 F
2
of the DRAM. Besides, compared with the ferroelectric random access memory (FRAM), such as an example described in “Novel Integration Technologies for Highly Manufacturable 32 Mb FRAM”, VLSI 2002 by H. H. Kim, et al., the bit size of the FRAM has decreased to 15 F
2
. Therefore, it is obvious that the MRAM has fallen behind the DRAM and FRAM. Recently, an improved structure for the MRAM has been disclosed in U.S. Pat. No. 6,421,271, in which MTJ cells are connected in parallel to a transistor such that the MRAM is downsized. However, complicated reading process such as back-writing method (commonly used in DRAM) is required for successfully accessing the data state, therefore, it significantly reduces the operation speed and is hard to replace the static random access memory (SRAM).
Please refer to
FIG. 1
, it shows a schematic diagram of a conventional MRAM comprising an MTJ cell and a transistor according to U.S. Pat. No. 5,734,605. As shown in
FIG. 1
, the first write word line W
1
and the second write word line W
2
are perpendicular to and crisscross with the first bit line S
1
and the second bit line S
2
. And a plurality of MTJ cells
11
and transistors
13
are disposed between the write word lines and the bit lines. Each MRAM cell is composed of an MTJ cell
11
and a transistor
13
(i.e. 1T1MTJ structure). Since the transistor includes a source, a drain, a gate, and an isolation, etc., the transistor occupies a large area when desinging the layout. The memory cell area of this kind of structure is about 20F
2
, not comparable with the DRAM. Therefore, it is not competitive.
Please refer to
FIG. 2
, it shows a schematic diagram of a conventional MRAM with a plurality of MTJ cells and a transistor according to U.S. Pat. No. 6,421,271. As shown in
FIG. 2
, a plurality of MTJ cells
20
are connected in parallel with each other and also connected to a transistor, therefore, significantly increasing the density. The gate of the first transistor Tr
1
connects to the first read word line WL
1
, and the drain of the first transistor Tr
1
connects to a plurality of MTJ cells
20
that are connected in parallel with each other. The gate of the second transistor Tr
2
connects to the second read word line WL
2
, and the drain of the transistor Tr
2
also connects to other MTJ cells
20
that are connected in parallel with each other, and use the same bit line BL with those MTJ cells
20
connected to the first transistor Tr
1
. However, since readout signal of the bit line is the equivalent resistance after the MTJ cells
20
are connected in parallel, it needs an additional readout process to filter the complex signals. The additional readout process requires destructive reading process, resulting in poor endurance of the memory cells and reducing the readout speed.
Accordingly, the present invention provides an MRAM to improve the drawbacks of uncapable of reducing size and increasing readout speed. The invention uses two bits to share one transistor and uses two MTJ cells with different resistance characteristics, which are connected in parallel or in series, so as to increase the package density and the readout speed, and to be a unified memory in replace of the conventional Flash, SRAM, and DRAM.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the present invention is to provide a high density MRAM with reduced size. In the MRAM, by using the multi-layered magnetic materials with different resistance characteristics, the magnetic tunnel junction cells are connected in parallel or in series, which are connected to a transistor, so as to be a control element for reading data. And there is a write word line for providing the magnetic field of the writing operation for a plurality of MTJ cells. Besides, there is a read word line for controlling the readout signal. Further, there is a plurality of bit lines for reading the data. Therefore, the present invention can increase the packing density and provide a unified memory in replace of the conventional Flash, SRAM, and DRAM.


REFERENCES:
patent: 5734605 (1998-03-01), Zhu et al.
patent: 6421271 (2002-07-01), Gogl et al.
patent: 6570783 (2003-05-01), Deak
patent: 6633497 (2003-10-01), Nickel
patent: 6646910 (2003-11-01), Bloomquist et al.

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