Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-06
2003-12-16
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S003000, C257S009000, C257S285000, C257S300000, C365S171000, C365S173000, C365S066000
Reexamination Certificate
active
06664579
ABSTRACT:
BACKGROUND
1. Technical Field
A magnetic random access memory and a method for fabricating the same are disclosed, and in particular technologies for fabricating a magnetic random access memory (abbreviated as ‘MRAM’) that has higher speeds than static random access memory (SRAM), integration as high as dynamic random access memory (DRAM), and properties of a nonvolatile memory such as a flash memory are disclosed.
2. Description of the Background Art
Many semiconductor memory manufacturing companies have been developing MRAM's using a ferromagnetic material as one of the next generation of memory devices. The MRAM, in particular, is a memory device for reading and writing information by forming multi-layer ferromagnetic thin films, and sensing current variations according to a magnetization direction of the respective thin films. The MRAM has high speed, low power consumption and high integration density due to the special properties of the magnetic thin film, and performs a nonvolatile memory operation such as a flash memory.
In its function as a memory device, the MRAM utilizes a giant magneto resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) generated when the spin influences electron transmission.
MRAM's using GMR utilize a phenomenon in which resistance is remarkably varied when spin directions are different in two magnetic layers having a non-magnetic layer disposed between the two magnetic layers.
MRAM's using SPMT utilize a phenomenon in which larger current transmission is generated when spin directions are identical in two magnetic layers having an insulating layer disposed therebetween.
MRAM research, however, is still in the early stages, and is concentrated mostly on the formation of multi-layer magnetic thin films and less on the research of unit cell structure and peripheral sensing circuits.
FIG. 1
is a cross-sectional diagram illustrating a conventional MRAM. As shown, a gate electrode
33
, namely a first word line, is formed on a semiconductor substrate
31
. Here, a gate oxide film
32
is formed on an interface between the gate electrode
33
and the semiconductor substrate
31
.
Source/drain junction regions
35
a
and
35
b
are formed in the semiconductor substrate
31
on both sides of the first word line
33
, and a reference voltage line
37
a
and a first conductive layer
37
b
are formed to contact the source/drain junction regions
35
a
and
35
b
. Here, the reference voltage line
37
a
is formed in the formation process of the first conductive layer
37
b.
Thereafter, a first interlayer insulating film
39
is formed to planarize the whole surface of the resultant structure, and a first contact plug
41
is formed to contact the first conductive layer
37
b.
A second conductive layer which is a lower read layer
43
contacting the first contact plug
41
is patterned.
A second interlayer insulating film
45
is formed to planarize the whole surface of the resultant structure, and a second word line
47
, which is a write line, is formed on the second interlayer insulating film
45
.
A third interlayer insulating film
48
is formed to planarize the upper portion of the second word line
47
, which is the write line. A second contact plug
49
is then formed to expose the second conductive layer
43
.
A seed layer
51
is formed to contact the second contact plug
49
. Here, the seed layer
51
is formed to overlap between the upper portion of the second contact plug
49
and the upper portion of the write line
47
. An additional interlayer insulating film
53
is also formed.
Thereafter, a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer
55
, a tunnel barrier layer
57
and a free ferromagnetic layer
59
are stacked on the seed layer
51
, thereby forming a magnetic tunnel junction (MTJ) cell
100
to have a pattern size as large as the write line
47
and to overlap the write line
47
.
At this time, the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer
55
from being changed, with the magnetization direction of the pinned ferromagnetic layer
55
fixed to one direction. The magnetization direction of the free ferromagnetic layer
59
can be changed by a generated magnetic field, and information of ‘0’ or ‘1’ can be stored according to the magnetization direction of the free ferromagnetic layer
59
.
A fourth interlayer insulating film
60
is formed over the resultant structure, and evenly etched to expose the free ferromagnetic layer
59
. An upper read layer, namely a bit line
61
is formed to contact the free ferromagnetic layer
59
.
Still referring to
FIG. 1
, the structure and operation of the MRAM will now be explained. The unit cell of the MRAM includes one field effect transistor having the first word line
33
as a read line for reading information, the MTJ cell
100
, the second word line
47
, which is a write line determining the magnetization direction of the MTJ cell
100
by forming an external magnetic field by applying current, and the bit line
61
which is an upper read layer informing the magnetization direction of the free layer by applying current to the MTJ cell
100
in a vertical direction.
Here, during the operation of reading the information from the MTJ cell
100
, a voltage is applied to the first word line
33
as the read line, thereby turning the field effect transistor on, and the magnetization direction of the free ferromagnetic layer
59
in the MTJ cell
100
is detected by sensing a magnitude of current applied to the bit line
61
.
During the operation of storing the information in the MTJ cell
100
, while maintaining the field effect transistor in off state, the magnetization direction in the free ferromagnetic layer
59
is controlled by a magnetic field generated by applying current to the second word line
47
, which is the write line, and the bit line
61
. At this time, when current is applied to the bit line
61
and the write line
47
at the same time, one cell can be selected in a vertical intersecting point of the two metal lines.
Further, the operation of the MTJ cell
100
in the MRAM will be described as follows. When the current flows in the MTJ cell
100
in a vertical direction, a tunneling current flows through an insulating film
60
. This tunneling current increases when the tunnel barrier layer
57
and the free ferromagnetic layer
59
have the same magnetization direction. When the tunnel barrier layer
57
and the free ferromagnetic layer
59
have different magnetization directions, the tunneling current decreases due to a tunneling magneto resistance (TMR) effect. A decrease in the magnitude of the current due to the TMR effect is sensed, and thus the magnetization direction of the free ferromagnetic layer
59
is sensed, thereby detecting the information stored in the cell.
FIG. 2
is a cross-sectional diagram illustrating a second example of a conventional MRAM. In the example shown in
FIG. 2
, an element isolating film (not shown) defining an active region is formed on a semiconductor substrate
111
. A gate electrode
113
having a gate oxide film
112
is formed on the active region of the semiconductor substrate
111
, an insulating film spacer (not shown) is formed at the side walls thereof, and source/drain regions
115
a
and
115
b
are formed by implanting an impurity to the active region of the semiconductor substrate
111
, thereby forming a transistor. The gate oxide film
112
is positioned on an interface between the gate electrode
113
and the semiconductor substrate
111
.
The effect of magnetic field is increased as the distance between the MTJ cell of the MRAM and the gate electrode
113
used as the write line becomes shorter. Accordingly, an interlayer insulating film is formed in a succeeding process in a reduced thickness.
The gate electrode
113
has a stacked structure of a polysilicon film/metal film, a polysilicon film/metal film/polysilicon film, a polysilicon film/silicide (CoSi
x
, TiSi
x
, etc.) film, or a polysilicon film/sili
Kang Hee Bok
Kim Chang Shuk
Lee Sun Ghil
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nelms David
Tran Mai-Huong
LandOfFree
Magnetic random access memory using bipolar junction transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Magnetic random access memory using bipolar junction transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Magnetic random access memory using bipolar junction transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3104935