Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-04
2001-02-06
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S207000, C365S209000, C365S205000, C365S202000, C365S171000, C365S173000
Reexamination Certificate
active
06185143
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to random access memory for data storage. More specifically, the present invention relates to a magnetic random access memory device including an array of memory cells and sense amplifiers for sensing resistance of the memory cells.
Magnetic Random Access Memory (“MRAM”) is a non-volatile memory that is being considered for long term data storage. Performing read and write operations in MRAM devices would be orders of magnitude faster than performing read and write operations in conventional long term storage devices such as hard drives. In addition, the MRAM devices would be more compact and would consume less power than hard drives and other conventional long term storage devices.
A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
A memory cell stores a bit of information as an orientation of a magnetization. The magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “0” and “1.”
The magnetization orientation affects the resistance of a memory cell such as a spin-tunneling device. For instance, resistance of a memory cell is a first value R if the magnetization orientation is parallel, and the resistance of the memory cell is increased to a second value R+&Dgr;R if the magnetization orientation is changed from parallel to anti-parallel. The magnetization orientation of a selected memory cell and, therefore, the logic state of the memory cell may be read by sensing the resistance state of the memory cell.
The resistance state may be sensed by applying a voltage to a selected memory cell and measuring a sense current that flows through the memory cell. Ideally, the resistance would be proportional to the sense current.
However, sensing the resistance state of a single memory cell in the array can be unreliable. All memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns (the array of memory cells may be characterized as a cross point resistor network).
Moreover, if the memory cell being sensed has a different resistance due to the stored magnetization, a small differential voltage may develop. This small differential voltage can give rise to a parasitic or “sneak path” current. The parasitic current is typically much larger than the sense current and, therefore, can obscure the sense current. Consequently, the parasitic current can prevent the resistance from being sensed.
Unreliability in sensing the resistance is compounded by manufacturing variations, variations in operating temperatures, and aging of the MRAM devices. These factors can cause the average value of resistance in the memory cell array to vary by a factor of two or three.
There is a need to reliably sense the resistance states of memory cells in MRAM devices.
SUMMARY OF THE INVENTION
These needs are met by the present invention. According to one aspect of the present invention, apparatus for sensing a resistance state of a selected memory cell in an MRAM device includes a differential amplifier having sense and reference nodes; a first current mode preamplifier coupled between the selected memory cell and the sense node of the differential amplifier; a reference cell; and a second current mode preamplifier coupled between the reference cell and the reference node of the differential amplifier.
REFERENCES:
patent: 4633443 (1986-12-01), Childers
patent: 5831920 (1998-11-01), Chen et al.
patent: 5898612 (1999-04-01), Chen et al.
patent: 5982658 (1999-11-01), Berg et al.
Eldredge Kenneth I
Perner Frederick A
Tran Lung T
Hewlett--Packard Company
Tho
Tran Andrew Q.
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