Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-25
2003-11-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C365S209000, C365S225500, C365S243500
Reexamination Certificate
active
06649953
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a magnetic random access memory (hereinafter MRAM) having a vertical structure transistor and, more particularly, to a MRAM having a faster access time than SRAM, a high density like that of DRAM, and a non-volatility like a flash memory device.
BACKGROUND OF THE INVENTION
As one of the next generation memory devices, MRAMs using a ferromagnetic material have been proposed by some semiconductor memory manufacturing companies. The MRAM is a memory device for reading and writing information that relies upon forming multi-layer ferromagnetic thin films and sensing current variations that depend upon the magnetization direction of the respective thin films. The MRAM device offers a high speed and low power consumption, and it allows for high integration density because of the special properties of the magnetic thin film. It also performs a nonvolatile memory operation, like a flash memory device.
Memory storage in a MRAM is achieved by using a giant magneto-resistive (abbreviated as ‘GMR’) phenomenon or a spin-polarized magneto-transmission (SPMT) in which spin influences electron transmission. GMR devices rely upon the variation in resistance that occurs when spin directions for two magnetic layers, having a non-magnetic layer therebetween, are different.
The SPMT technique utilizes the phenomenon that larger currents are transmitted when spin directions are identical in two magnetic layers, having an insulating layer therebetween. This is used to create a magnetic permeable junction memory device.
Despite these techniques, the MRAM research is still in its early stages, and mostly concentrated on the formation of multi-layer magnetic thin films. Little research is performed on unit cell structure or the peripheral sensing circuit.
FIG. 1
is a cross-sectional diagram illustrating a conventional MRAM. Shown is a gate electrode
33
, i.e., a first word line, that has been formed on a semiconductor substrate
31
. Source/drain junction regions
35
a
and
35
b
are formed on the semiconductor substrate
31
on both sides of the first word line
33
, respectively. A ground line
37
a
and a first conductive layer
37
b
are formed to contact the source/drain junction regions
35
a
and
35
b
, respectively. Here, the ground line
37
a
is formed during the patterning process that forms the first conductive layer
37
b.
Thereafter, a first interlayer insulating film
39
is formed to planarize the whole surface of the resultant structure, and a first contact plug
41
is formed to contact the first conductive layer
37
b
, through the first interlayer insulating film
39
.
A second conductive layer, which is a lower read layer
43
contacting the first contact plug
41
, is patterned. A second interlayer insulating film
45
is formed to planarize the whole surface of the resultant structure, and a second word line, which is a write line
47
, is formed on the second interlayer insulating film
45
. A third interlayer insulating film
48
is formed to planarize the upper portion of the second word line
47
.
A second contact plug
49
is formed to contact the second conductive layer
43
. A seed layer
51
is formed to contact the second contact plug
49
. Here, the seed layer
51
is formed to overlap between the upper portion of the second contact plug
49
and the upper portion of the write line
47
. Then, a fourth interlayer insulation layer
53
is formed and planarized to expose the seed layer
51
. Thereafter, a semi-ferromagnetic layer (not shown), a pinned ferromagnetic layer
55
, a tunnel junction layer
57
, and a free ferromagnetic layer
59
are stacked on the seed layer
51
, thereby forming a magnetic tunnel junction (MTJ) cell
100
having a pattern size as large as the write line
47
and overlapping the write line
47
in location.
At this time, the semi-ferromagnetic layer prevents the magnetization direction of the pinned layer
55
from changing, and the magnetization direction of the tunnel junction layer
57
is fixed to one direction. The magnetization direction of the free ferromagnetic layer
59
can be changed by application of an external magnetic field, and a ‘0’ or ‘1’ bit can be stored by the device according to the magnetization direction of the free ferromagnetic layer
59
. A fifth interlayer insulation layer
60
is formed on the whole surface and planarized to expose the free ferromagnetic layer
59
, and an upper read layer, i.e., bit line
61
connected to free ferromagnetic layer
59
is formed.
In operation, the unit cell of the MRAM includes one field effect transistor formed of the first word line
33
, which is a read line used to read information, the MTJ cell
100
, and the second word line
47
. The second word line
47
is a write line that determines the magnetization direction of the MTJ cell
100
by applying a current to form an external magnetic field. The field effect transistor also includes the bit line
61
, which is an upper read layer for determining the magnetization direction of the free ferromagnetic layer
59
by applying a current to the MTJ cell
100
that flows in a vertical direction.
To read the information from the MTJ cell
100
, a voltage is applied to the first word line
33
, as the read line. This turns the field effect transistor on, and, by sensing the magnitude of the current applied to the bit line
61
, the magnetization direction of the free ferromagnetic layer
59
in the MTJ cell
100
is detected and its state read.
During storage of information in the MTJ cell
100
, the field effect transistor is in an off state and the magnetization direction in the free ferromagnetic layer
59
is controlled by a magnetic field generated by applying current to the second word line
47
, which is the write line, and to the bit line
61
. When current is applied to the bit line
61
and the write line
47
at the same time, the generated magnetic field is strongest at a vertical intersecting point of the two metal lines. This may be used to select one cell from a plurality of cells, for example.
The operation of the MTJ cell
100
in the MRAM will now be described. When the current flows in the MTJ cell
100
in a vertical direction, a tunneling current flows through an interlayer insulating film. When the tunnel junction layer
57
and the free ferromagnetic layer
59
have the same magnetization direction, this tunneling current increases. When the tunnel junction layer
57
and the free ferromagnetic layer
59
have different magnetization directions, however, the tunneling current decreases due to a tunneling magneto resistance (TMR) effect. A decrease in the magnitude of the tunneling current due to the TMR effect is sensed, and, thus, the magnetization direction of the free ferromagnetic layer
59
is sensed, which thereby detects the information stored in the MTJ cell
100
.
As described above, the conventional MRAM comprises a horizontal structure transistor having the write line as the second word line and the MTJ cell in a vertical stack on an upper portion of the transistor. In order to form the MRAM, surface roughness in the lower part of the device, where the MTJ cell is formed, should be controlled within nanometer tolerances. However, since there is a second word line and contact lines below the MTJ cell it is difficult to prevent surface roughness on the lower part of the device to within nanometer ranges.
Since the structure of a MRAM device is more complex than that of DRAM, as a whole, the MRAM requires a total of four metal lines per unit cell, i.e., two word lines, one bit line, and a ground line. MRAMs using the MTJ cell could potentially offer high integration, i.e., integration on the order of several to 100 gigabits To achieve this, increasing a short channel effect of a transistor and control of resistance are important factors. However, the resistance is more difficult to control as the size of the transistor becomes smaller, and the resistance of the transistor together with that of the MTJ cell has a great influence on cell operat
Hynix Semiconductor Inc
Marshall & Gerstein & Borun LLP
Nelms David
Tran Long
LandOfFree
Magnetic random access memory having a transistor of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Magnetic random access memory having a transistor of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Magnetic random access memory having a transistor of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3156352