Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2001-05-15
2002-01-22
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06341084
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a random access memory circuit, and more specifically to a magnetic random access memory circuit (called a “MRAM circuit” in this specification).
A magnetic random access memory includes a plurality of memory cells located at intersections of word lines and bit lines, each memory cell being basically constituted of a pair of ferromagnetic layers separated by an insulating or non-magnetic metal layer. Digital information is represented by the direction of magnetic vectors in the ferromagnetic layers, and is infinitely maintained unless it is intentionally rewritten. In order to write or change the state of the memory cell, a composite magnetic field which is generated by use of a word current and a bit current and which is larger than a threshold, is applied to the memory cell, so as to reverse the magnetization of the ferromagnetic layers.
U.S. Pat. No. 5,748,519 and IEEE Transaction On Components Packaging and Manufacturing Technology—Part A, Vol. 170, No. 3, pp373-379 (the content of which are incorporated by reference in its entirety into this application) disclose a first example of the magnetic random access memory which includes a number of memory cells configured to utilize a giant magneto-resistive (GMR) effect. Referring to
FIG. 1
, there is shown a layout diagram of a simplified MRAM circuit including each memory cell configured to utilize the GMR effect. The MRAM circuit is conventionally formed on a semiconductor substrate on which other circuits are formed, so that the MRAM circuit and other circuits are formed on the same substrate in a mixed condition. As shown in
FIG. 1
, the MRAM circuit includes a memory array divided into a first array portion
604
and a second array portion
605
, a decoder consisting of a row decoder
602
and a column decoder
603
, and a comparator
606
. The row decoder
602
and the column decoder
603
are connected to an address bus
601
, respectively. In a reading operation, one of the first array portion
604
and the second array portion
605
is used as a reference cell. In each array portion, a plurality of GMR elements are connected in series in each one row. In the reading operation, a current is caused to flow in a selected row of each of the first array portion
604
and the second array portion
605
, a difference between respective voltages generated in the first array portion
604
and the second array portion
605
is detected by the comparator.
U.S. Pat. No. 5,640,343 (the content of which is incorporated by reference in its entirety into this application) discloses a second example of the magnetic random access memory includes a number of memory cells configured to utilize a magnetic tunnel junction (MTJ) effect. Referring to
FIG. 2
, there is shown a MRAM circuit including each memory cell configured to utilize the MTJ effect. The shown MRAM circuit includes row decoders
701
and
702
, column decoders
703
and
704
, and a matrix circuit having a number of MTJ elements
711
to
715
and so on located at intersections of word lines
705
,
706
and
707
extending between the row decoders
701
and
702
and bit lines
708
,
709
and
710
extending between the column decoders
703
and
704
. In this MRAM circuit, a stored information is distinguished dependent upon whether a sense current is large or small. However, this patent does not disclose a method for detecting the magnitude (large or small) of the sense current, nor does it show how to connect a comparator (sense amplifier).
In this first prior art example, a resistance of serially connected memory cells is directly detected. However, the resistance detected includes an on-resistance of a transistor connected in series with the row. In addition, a memory cell array and a reference cell array are separated or put apart from each other. Therefore, a reference signal is inclined to contain a parasite component, with the result that it is difficult to have a sufficient margin in operation. Accordingly, a high level of equality in characteristics is required for memory cells on the same wafer. In addition, since it is so configured to detect the voltage of a plurality of serially connected memory cells, a magnetically changed component of the resistance is small in comparison with the resistance of the whole of the row, with the result that a device variation and a noise resisting property are deteriorated. Furthermore, in order to make the detecting sensitivity large, it is necessary to enlarge a detecting current or to bring the GMR element into an elongated form so as to increase the device resistance This results in an increased power consumption and in an increased circuit area.
In the second prior art example, each memory cell includes a diode. Similarly, each memory cell can be easily constructed to include a transistor. In the memory cell including the diode or the transistor, however, the cell construction becomes complicated, and therefore, is difficult to integrate the circuit. On the other hand, it is not so easy to construct a two-dimensional array with only the magneto-resistive elements which cannot operate as a complete on-off switch, because a detouring of the current in the cells must be considered.
Furthermore, in conventional GMR elements, since the current is caused to flow in parallel to a film surface, a fundamental resistance is equivalent to a wiring resistance. Accordingly, if a wiring conductor, a transistor and a magneto-resistive element are connected in series and the voltage of the whole of the series-connected circuit is directly measured, a voltage drop occurring across the wiring conductor and the transistor is not negligible, and a highly precise reading circuit (sense amplifier) becomes necessary.
Journal of Magnetics Society of Japan, Vol. 23, No. 1-2, pp55-57 mentions that a tunnel magneto-resistive element (TMR element) has such a feature that when a voltage applied between opposite ends of the junction increases, the magneto-resistive ratio (MR ratio) decreases. This is generally called a bias effect and is well known to persons skilled in the art. Because of this bias effect, even if a large voltage is applied across the TMR element, the changed component of the device voltage caused by a magnetic field does not necessarily proportionally become large. Therefore, a highly precise reading circuit becomes necessary.
Journal of Magnetism and Magnetic Materials, Vol. 198-199, No. 1-2, pp164-166 mentions that a large voltage is applied between opposite ends of the TMR element having a thin tunnel barrier, there is a problem in which a tunnel barrier is broken by an electric field and heat, so that a device lift is shortened.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an MRAM circuit having a large operation margin, by eliminating influence of variation in characteristics of magneto-resistive elements depending upon a geographical location on the same wafer, to the utmost.
Another object of the present invention is to provide a highly sensitive MRAM circuit capable of reading at a high speed, by preventing a lowering of the detecting sensitivity of a reading circuit, attributable to a voltage drop caused by the resistance of the wiring conductor and the transistor connected in series with the magneto-resistive element.
Still another object of the present invention is to provide an MRAM circuit having a tunnel type magneto-resistive element, which is a highly sensitive and can be read at a high speed, by preventing the bias effect of the magneto-resistance and the breakage of the tunnel barrier.
A further object of the present invention is to provide an MRAM circuit which can be integrated with a high integration density, by eliminating the diode or the transistor in the basic memory cell.
The above and other objects of the present invention are achieved in accordance with the present invention by a magnetic random access memory circuit comprising:
a memory cell array having a plurality of sense lines, a plu
Numata Hideaki
Takeda Kouichi
NEC Corporation
Phan Trong
Sughrue & Mion, PLLC
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