Magnetic random access memory circuit

Details Magnetic random access memory circuit Magnetic random access memory circuit

2000-05-01

2001-02-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S158000, C365S175000, C365S189080

Reexamination Certificate

active

06191972

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a magnetic random access memory circuit (called a “MRAM circuit” in this specification).
A magnetic random access memory includes a plurality of memory cells located at intersections of word lines and bit lines, each memory cell being basically constituted of a pair of ferromagnetic layers separated by an insulating or non-magnetic metal layer. Digital information is represented by the direction of magnetic vectors in the ferromagnetic layers, and is infinitely maintained unless it is intentionally rewritten. In order to write or change the state of the memory cell, a composite magnetic field which is generated by use of a word current and a bit current and which is larger than a threshold, is applied to the memory cell, so as to reverse the magnetization of the ferromagnetic layers.
A first example of the magnetic random access memory includes a number of memory cells configured to utilize a giant magneto-resistive (GMR) effect, as disclosed by U.S. Pat. No. 5,748,519 and IEEE Transaction On Components Packaging and Manufacturing Technology—Part A Vol. 170, No. 3, pp373-379 (the content of which are incorporated by reference in its entirety into this application). Referring to
FIG. 1
, there is shown a layout diagram of a simplified MRAM circuit including each memory cell configured to utilize the GMR effect. As shown in
FIG. 1
, the MRAM circuit includes a memory array divided into a first array portion
604
and a second array portion
605
, a decoder consisting of a row decoder
602
and a column decoder
603
, and a comparator
606
. The row decoder
602
and the column decoder
603
are connected to an address bus
601
, respectively. In a reading operation, one of the first array portion
604
and the second array portion
605
is used as a reference cell.
In this first prior art example, separate word lines are required for a memory cell and a reference cell, respectively, and a memory cell array and a reference cell array are separated or put apart from each other. Therefore, a reference signal is inclined to contain a parasite component, with the result that it is difficult to have a sufficient margin in operation. Accordingly, a high level of equality in characteristics is required for memory cells on the same wafer. In addition, since the separate word lines are required for a memory cell and a reference cell, respectively, and since the memory cell array and the reference cell array are separated apart from each other, a memory cell area is large, so that it is difficult to elevate the integration density for microminiaturization.
Furthermore, in this first prior art example, since two cells (one included in the first array portion
604
and another included in the second array portion
605
) are required for one address, a memory cell area is large, so that it is difficult to elevate the integration density for microminiaturization.
A second example of the magnetic random access memory includes a number of memory cells configured to utilize a magnetic tunnel junction (MTJ) effect, as disclosed by U.S. Pat. No. 5,640,343 (the content of which is incorporated by reference in its entirety into this application). Referring to
FIG. 2
, there is shown a MRAM circuit including each memory cell configured to utilize the MTJ effect. The shown MRAM circuit includes row decoders
701
and
702
, column decoders
703
and
704
, and a matrix circuit having a number of MTJ elements
711
to
715
and so on located at intersections of word lines
705
,
706
and
707
extending between the row decoders
701
and
702
and bit lines
708
,
709
and
710
extending between the column decoders
703
and
704
. In this MRAM circuit, a stored information is distinguished dependent upon whether a sense current is large or small. However, this patent does not disclose a method for detecting the magnitude (large or small) of the sense current, nor does it show how to connect a comparator (sense amplifier).
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an MRAM circuit which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide an MRAM circuit having a characteristics which does not depend upon variation in characteristics of magneto-resistive elements depending upon a geographical location on the same wafer.
Still another object of the present invention is to provide an MRAM circuit capable of reading at high sensitivity while excluding influence of a wiring resistance to the utmost.
A further object of the present invention is to provide an MRAM circuit having a circuit construction effective for integration.
The above and other objects of the present invention are achieved in accordance with the present invention by a magnetic random access memory circuit comprising:
a row decoding means receiving a part of a given address;
a column decoding means receiving the other part of a given address;
a plurality of pairs of sense lines connected to output terminals of the row decoding means, each pair of sense lines being located adjacent to each other;
a plurality of word lines connected to output terminals of the column decoding means, the word lines extending to intersect the sense lines so that intersections of the sense lines and the word lines are located in the form of a matrix;
a memory array including a plurality of cell pairs distributed over the matrix, each cell pair including a memory cell and a reference cell located adjacent to each other, each of the memory cell and the reference cell including a magneto-resistive element;
the memory cell and the reference cell of each cell pair being located at intersections of one word line and one pair of sense lines, respectively, the memory cell of the each cell pair being connected between one sense line of the one pair of sense lines and the one word line, and the reference cell of the each cell pair being connected between the other sense line of the one pair of sense lines and the one word line.
In a specific embodiment of the magnetic random access memory circuit, the row decoding means includes a pair of row decoders each receiving the part of a given address, and the column decoding means includes a pair of column decoders each receiving the other part of a given address, each of the sense lines being connected between one output of plural outputs of one row decoder of the pair of row decoders and a corresponding output of plural outputs of the other row decoder of the pair of row decoders, each of the word lines being connected between one output of plural outputs of one column decoder of the pair of column decoders and a corresponding output of plural outputs of the other column decoder of the pair of column decoders.
In a writing operation, the pair of row decoders supply one selected pair of sense lines with an electric current which flows in a direction corresponding to the value of a binary information to be written, and the pair of column decoders supply an electric current of a predetermined direction regardless of the value of the binary information to be written, in a selected word line of the word lines.
On the other hand, in a reading operation, the row decoding means and the column decoding means flow the same current in the memory cell and the reference cell of a selected cell pair to be read out.
In a preferred embodiment, the magnetic random access memory circuit further includes a comparing means for comparing a potential at a sense line side terminal of the memory cell of the selected cell pair with a potential of a sense line side terminal of the reference cell of the selected cell pair.
Specifically, the comparing means includes a comparator having a non-inverted input and an inverted input, first and second subsidiary lines connected to the non-inverted input and the inverted input of the comparator, respectively, a plurality of first switch transistors each having one end connected in common to the first subsidiary line and the other end

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