Magnetic memory device

Details Magnetic memory device Magnetic memory device

2000-12-14

2002-10-29

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S158000

Reexamination Certificate

active

06473336

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an information recording technique using a ferromagnetic material, particularly to a magnetic memory device utilizing magnetic tunnel junction.
A magnetic random access memory (hereinafter, abbreviated as MRAM) is a type of a solid state memory that can rewrite, hold, and read out record information any time by utilizing a magnetization direction of the ferromagnetic material as an information recording medium. This MRAM records information by corresponding binary coded information “1” and “0” whether the magnetization direction of the ferromagnetic material is parallel to or anti-parallel to a reference direction.
Recording information is written by switching the magnetization direction of the ferromagnetic material of each cell by a magnetic field generated by supplying a current to a write line disposed in a cross stripe shape. The power consumption during storing is principally zero.
Stored information is read out by utilizing a phenomenon in which the electric resistance of a memory cell changes depending on a relative angle between the magnetization direction of the ferromagnetic material that configures cells and a direction of a sense current or depending on a relative angle of magnetization between a plurality of ferromagnetic layers, so called the magnetoresistance effect.
The MRAM has the following advantages in comparison with a conventional semiconductor memory.
(a) Completely non-volatile. 10
15
or more endurance cycles are possible.
(b) Nondestructive readout is possible, and refresh operation is not required, thus making it possible to reduce a readout cycle.
(c) The durability against radiation is strong in comparison with a charge storage type memory cell.
The degree of integration per a unit area for the MRAM and the write and readout times are expected to be approximately equal to those of the DRAM. Therefore, it is further expected to apply the MRAM to an external memory device for a portable digital audio instrument, a wireless IC card, and a mobile personal computer (PC) by utilizing significant non-volatile characteristics.
In an MRAM having its recording capacity of 1 Mb that is currently discussed for practical use, a Giant Magnetoresistance (hereinafter, abbreviated as a GMR effect) is employed for reading out stored information. An example of such an MRAM cell using an element that indicates the GMR effect (hereinafter, abbreviated as the GMR element), is disclosed in IEEE Trans. Mag., 33,3289 (1997)).
A value of the GMR effect of the tri-layered film made of a non-coupling NiFe/Cu/Co is about 6% to 8%. For example, in the aforementioned MRAM cell using the PseudoSpin-Valve structure, the distribution of the magnetic direction during readout of recorded information is controlled, whereby the resistance change of 5% or more is effectively obtained. However, in general, the sheet resistance of the GMR element is about some tens &OHgr;/&mgr;m
2
. Therefore, even in the case where the sheet resistance of 100 &OHgr;/&mgr;m
2
and the resistance change rate of 5% are assumed, the output signal relevant to a sense current of 10 mA is merely 5 mV. Currently, in a MOS type field effect transistor that is practically available for use, the value of a source/drain current Ids is proportional to a rate between a channel width W and a channel length L, and the value of Ids when W=3.3 &mgr;m and L=1 &mgr;m is about 0.1 mA. Therefore, the value of the sense current of 10 mA used here is very excessive relevant to a transistor with sub-micron dimensions.
In order to solve this problem, in the MRAM cell using the GMR element, there is employed a method of connecting a plurality of GMR elements in series, and then, configuring a data lie (for example, refer to IEEE Trans. Comp. Pac. Manu. Tech. pt. A, 17,373 (1994).). However, in the case where memory cells are connected in series, there is a disadvantage that the power consumption efficiency during readout is greatly lowered.
In order to solve these problems, there is proposed an attempt to apply a ferromagnetic tunnel effect (Tunnel Magnetoresistance: hereinafter, abbreviated as a TMR effect) instead of the GMR effect. An element indicating the TMR effect (hereinafter, abbreviated as the TMR element) is primarily composed of a tri-layered film made of a ferromagnetic layer
1
, an insulating layer, and a ferromagnetic layer
2
, and current tunnels through the insulating barrier. The tunnel resistance value changes in proportion to a cosine of a relative angle in magnetization of both of the ferromagnetic metal layer, and an maximum value is obtained in the case where one magnetization is antiparallel to another.
For example, in tunnel junction of NiFe/Co/Al
2
O
3
/Co/NiFe, the magnetoresistance ratio exceeding 25% in a low magnetic field of 500e or less is found out (for example, refer to IEEE Trans. Mag., 33,3553 (1997)). The cell resistance value of the TMR element is typically between 10
4
ohms and 10
6
&OHgr; per a junction area (&mgr;m
2
). Therefore, assuming that the resistance value is 10 k&OHgr;, and the magnetoresistance ratio is 25% in a cell of 1 &mgr;m
2
, a cell readout signal of 25 mV is obtained in a sense current of 10 &mgr;A.
In an MRAM cell array using the TMR element, a plurality of TMR elements are connected in parallel on a data line. The following detailed structures are adopted.
(1) A structure in which a selection semiconductor element is disposed in series at each TMR element;
(2) A structure in which a selection transistor is disposed for each data line where a plurality of TMR elements are connected in parallel; and
(3) A structure in which a plurality of TMR elements are disposed in matrix, and a selection transistor is disposed for each row data line or each column data line (for example, refer to J. Appl. Phys., 81,3758 (1997)).
Among these structures, the structure of (1) has the most excellent characteristics in an aspect of power consumption efficiency during cell output voltage readout.
However, in the MRAM cell array having the structure of (1), it is required to supply a current to a semiconductor element connected to the TMR element during readout. As a semiconductor element, there are employed: a MOS type transistor; a diode element using the transistor; and a diode element using pn junction or Schottky junction. Therefore, in the case where there occurs dispersion in characteristics of these semiconductor elements, noise caused by such dispersion cannot be ignored.
For example, in the case of a MOS transistor, a voltage drop between a source and a drain reaches 100 mV or more in a rule of 0.25 &mgr;m. That is, if there exists a dispersion of 10% in characteristics of a semiconductor element, noise of 10 mV or more is generated by such dispersion. In addition, in consideration of a noise generated at a peripheral circuit such as noise coupled with data line or noise due to dispersion in characteristics of the sense amplifier, the noise level is greater than 10 mV. In a current cell output voltage of about 20 mV to 30 mV, an only signal-to-noise ratio of some decibels can be obtained.
In order to improve the signal-to-noise ratio, in a conventional MRAM cell array, there is often employed a method for comparing an output voltage V of a selected single memory cell with a reference V
REF
, thereby differentially amplifying a differential voltage V
sig
therebetween. A first object of this is to eliminate noise generated in a data line pair to which a memory cell connects, and a second object of this is to eliminate an offset of a cell output voltage V
sig
due to dispersion in characteristics of the semiconductor element for driving a sense line or selecting a cell. As a circuit for generating the reference voltage V
REF
, there are employed a circuit using the semiconductor element or dummy cell. However, in this method, the selected memory cell and the circuit for generating the reference voltage are connected to their respective cell selection semiconductor elements, making it impossible to complet

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