Magnetic memory capable of minimizing gate voltage stress in...

Details Magnetic memory capable of minimizing gate voltage stress in... Magnetic memory capable of minimizing gate voltage stress in...

2011-07-26

2011-07-26

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S189090, C365S173000, C365S171000, C365S158000, C365S190000

Reexamination Certificate

active

07986572

ABSTRACT:
Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.

REFERENCES:
patent: 5515314 (1996-05-01), Kouhei et al.
patent: 6285581 (2001-09-01), Tehrani et al.
patent: 6714390 (2004-03-01), Terada et al.
patent: 6754055 (2004-06-01), Ono et al.
patent: 6961265 (2005-11-01), Witcraft et al.
patent: 6985382 (2006-01-01), Fulkerson et al.
patent: 7046547 (2006-05-01), Witcraft et al.
patent: 2003/0090925 (2003-05-01), Demange et al.
patent: 2004/0100835 (2004-05-01), Sugibayashi et al.
patent: 2009/0168505 (2009-07-01), Hanzawa et al.
patent: 2009/0180310 (2009-07-01), Shimomura et al.
patent: 2011/0038200 (2011-02-01), Yang
International Search Report PCT/US 10/01896, Aug. 13, 2010, Magic Technologies, Inc.

Affiliated with

Also associated with

Rating

Magnetic memory capable of minimizing gate voltage stress in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Magnetic memory capable of minimizing gate voltage stress in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Magnetic memory capable of minimizing gate voltage stress in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2636817