Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-04-17
2004-07-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S068000, C257S071000, C257S296000, C257S298000, C257S326000, C257S529000, C257S530000, C438S003000, C438S240000, C438S131000, C438S132000, C438S215000, C438S281000, C438S601000
Reexamination Certificate
active
06768150
ABSTRACT:
BACKGROUND OF INVENTION
Ferromagnetic elements are used, for example, to form non-volatile memory cells.
FIG. 1
shows a conventional ferromagnetic memory cell
105
. As shown, the magnetic cell includes a magnetic element
106
having top and bottom magnetic layers
110
and
130
. The magnetic layers serve as electrodes of the magnetic element. The magnetic layers, for example, comprise cobalt-iron or nickel-cobalt-iron. A non-magnetic layer
120
separates the first and second magnetic layers. The non-magnetic layer, for example, comprises an insulating material, such as aluminum oxide, to form a magnetic tunnel junction (MTJ) type element.
First and second conductors
140
and
150
are coupled to the electrodes (e.g., top and bottom magnetic layers). One conductor is referred to as the bitline and the other is referred to as the wordline. The bitline and wordline are orthogonal to each other. A plurality of magnetic cells
105
are interconnected by wordlines
150
1−n
and bitlines
140
1−m
to form an array, as shown in FIG.
2
. Cells, depicted by the resistor symbols, are located at intersections of wordlines and bitlines.
The magnetic element is typically rectangular or elliptical in shape, having a width and length L. The magnetic layers of the cell are formed with an easy axis along the length L and a hard axis along the width. The magnetic vector in the bottom layer is fixed or pinned in a first direction parallel to the easy axis. The bottom layer with the fixed magnetic vector is referred to as the reference or fixed layer. The magnetic vector in the top magnetic layer can be switched between first and second (opposite) directions parallel to the easy axis. As such, the magnetic vectors in the layers can be oriented parallel or antiparallel to each other. The top magnetic layer with switchable magnetic vector is referred to as the storage or free layer.
The direction of the vectors in the top layer can be switched by the application of a magnetic field generated by passing a current through one or both conductors. Depending on the magnetic field generated, the magnetic vector in the second layer either switches direction or remains the same. The magnetic element would have first and second resistance values based on whether the magnetic vectors are oriented parallel or anti-parallel, representing first and second logic states stored. For example, the magnetic element will have a high resistance value when the vectors of the layer are antiparallel to represent a logic 1 or a low resistance when the vectors are parallel to represent a logic 0. The states stored in the element can be read by passing a sense current through the element and sensing the difference between the resistances.
However, shorting across the non-magnetic layer of a cell, a common failure mode, creates a current path between the wordline and bitline to which the cell is coupled. Since the cell is not isolated from the wordline or bitline, the current path created by the shorted cell can render the array defective.
From the above discussion, it is desirable to reduce the adverse impact of a defective MRAM cell to the memory array.
SUMMARY OF INVENTION
The invention relates to magnetic memory cells. In one embodiment, a memory cell includes a magnetic element having first and second electrodes. A first conductor is coupled to the first electrode of the magnetic element. A second conductor is coupled to the second electrode of the magnetic element. In one embodiment, the second conductor is coupled to the second electrode via a conductive strap. The conductive strap produces a coupling which is offset by a distance x between the second conductor and magnetic element. The conductors can be formed from, for example, copper, aluminum, alloys or combination thereof. The conductive strap comprises, for example, tantalum nitride. A plurality of memory cells are interconnected by first and second conductors to form a memory array or block.
In accordance with the invention, the conductive strap comprises a fuse portion which can be severed to decouple the second conductor from the magnetic element. In one embodiment, the fuse portion comprises an electrically blowable fuse portion. The electrically blowable fuse portion can be blown by, for example, passing an elevated current through the strap. By providing the strap with a fuse portion, a magnetic element can be decoupled from the array by blowing the fuse portion.
REFERENCES:
patent: 6473337 (2002-10-01), Tran et al.
Low Kia Seng
Schmid Joerg Dietrich
Huynh Andy
Infineon Technologies Aktiengesellschaft
Nelms David
Slater & Matsil L.L.P.
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