Magnetic memory

Static information storage and retrieval – Systems using particular element – Magnetic thin film

Reexamination Certificate

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C365S158000, C365S171000

Reexamination Certificate

active

06717845

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2002-007877, filed on Jan. 16, 2002; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a magnetic memory, and more particularly, to a large-capacity high-speed magnetic memory having the integrated memory cells including magnetoresistance effect elements of a ferromagnetic tunneling type, for example, and reduced in cross talk between the memory cells while making a stable read-out and write-in with a reduced power consumption.
Magnetoresistance effect elements using magnetic films are currently used in magnetic heads, magnetic sensors, etc., and there is a proposal to use magnetoresistance effect elements in a solid-state magnetic memory (magnetoresistance memory or MRAM (magnetic random access memory)).
Recently, a so-called “tunneling magnetoresistance effect element (TMR element) has been proposed as a magnetoresistance effect element configured to flow a current perpendicularly to the film plane in a sandwich-structured film interposing a single dielectric layer between two magnetic metal layers and to use the tunneling current. Since tunneling magnetoresistance effect elements have been improved to ensure 20% or higher ratio of change in magnetoresistance (J. Appl. Phys. 79, 4724 (1996)), the possibility of civilian applications of MRAM is increasing.
A tunneling magnetoresistance effect element can be obtained by first forming a thin Al (aluminum) layer, 0.6 nm through 2.0 nm thick, on a ferromagnetic electrode, and thereafter exposing its surface to a glow discharge of oxygen or oxygen gas to form a tunnel barrier layer of Al
2
O
3
.
There is also proposed a ferromagnetic single tunneling junction structure in which an anti-ferromagnetic layer is provided in one of the ferromagnetic layers on one side of the single ferromagnetic tunneling junction and the other ferromagnetic layer is used as a magnetically pinned layer (Japanese Patent Laid-Open Publication No. H10-4227).
Other type ferromagnetic tunneling junction structures, namely, one having a ferromagnetic tunneling junction via magnetic particles distributed in a dielectric material and one having double ferromagnetic tunneling junctions (continuous film) have been proposed as well (Phys. Rev. B56(10), R5747 (1997), J. The Magnetics Society of Japan 23, 4-2, (1999), Appl. Phys. Lett. 73(19), 2829 (1998), Jpn. J. Appl. Phys. 39, L1035(2001)).
Also these ferromagnetic tunneling junctions have been improved to ensure a ratio of magnetoresistance change from 20 to 50% and to prevent a decrease of the ratio of magnetoresistance change even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage, and there is the possibility of their applications to MRAM.
Magnetic recording elements using such a single ferromagnetic tunneling junction or double ferromagnetic tunneling junctions are nonvolatile and have high potentials such as high write and read speed not slower than 10 nanoseconds and programmable frequency not less than 10
15
times. Especially, ferromagnetic double-tunneling structures ensure large output voltages and exhibit favorable properties as magnetic recording elements because the ratio of magnetoresistance change does not decrease even upon an increase of the voltage value applied to tunneling magnetoresistance effect elements to obtain a desired output voltage value as mentioned above.
With regard to the memory cell size, however, those existing techniques involve the problem that the size cannot be decreased below semiconductor DRAM (dynamic random access memory) when a 1 Tr (transistor)-1 TMR architecture (disclosed, for example, in U.S. Pat. No. 5,734,605) is employed.
For overcoming the problem, there are proposals such as a diode-type architecture in which TMR cells and diodes are serially connected between bit lines and word lines (U.S. Pat. No. 5,640,343), and a simple-matrix architecture in which TMR cells are placed between bit lines and word lines (DE 19744095, WO 9914760).
However, in any case, the power consumption is large since magnetic reversal is preformed by a current magnetic field generated by a current pulse at the time of the writing, the number of integrated cells is limited since there is an allowable-current density limit of wiring, and the area of a driver circuit becomes large since the absolute value of write-in current may become as high as about 1 mA.
For this reason, there are many problems which should be improved for the conventional magnetic memories when compared with other non-volatilized solid state memories such as FeRAM (ferroelectric random access memory), a semiconductor flash memory, etc.
The solid magnetism storage in which a thin film made of a magnetic material of high permeability is provided in the surroundings of write-in wiring is proposed (U.S. Pat. No. 5,659,499, U.S. Pat. No. 5,956,267, the international patent application WO 00/10172, and U.S. Pat. No. 5,940,319).
According to such magnetic storage, since the high permeability magnetism film is provided in the circumference of wiring, a current required for the writing of the information on a magnetic-recording layer may be reduced.
However, in the magnetic storage which the U.S. Pat. No. 5,659,499 discloses, the magnetic field impressed to the record layer of a magnetoresistance effect film is uneven.
Moreover, when using the idea disclosed in the U.S. Pat. No. 5,956,267 and the U.S. Pat. No. 5,940,319, it is difficult to apply a magnetic field to a free layer efficiently with the structure where the free layer (record layer) is prepared in the central part of the magnetic layer which carried out laminating like a “dual spin valve type double tunnel junction.”
On the other hand, by the magnetic storage currently indicated in the international patent application WO 00/10172, although it has the structure where a big magnetic field can be impressed at the free layer, the manufacture becomes very difficult.
As a result of an original examination of this inventor, it became clear that the magnetization state of this covering layer is very important when the covering layer formed in the circumference of write-in wiring.
That is, when the magnetization state of a covering layer was not controlled, it became clear that the current magnetic field from write-in wiring could not be efficiently impressed to the record layer of a magnetoresistance effect element.
Moreover, it became clear that a bad influence may arise in writing or read-out, if an asteroid curve is deformed by a magnetic interaction between the covering layer and the adjacent magnetoresistance effect elements depending on the direction of magnetization of the covering layer.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, there is provided a magnetic memory comprising:
a magnetoresistance effect element having a magnetic recording layer;
a first wiring extending in a first direction on or below the magnetoresistance effect element;
a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and
a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
According to another embodiment of the invention, there is provided a magnetic memory comprising:
a first wiring extending in a first direction;
a magnetoresistance effect element provided on the first wiring and having a magnetic recording layer;
a second wiring extending in a direction across the first direction above the magnetoresistance effect element;
a covering layer provided on at least both sides of at least one of the first and second wirings, the covering laye

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