Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1998-08-06
2001-05-29
Etienne, Ario (Department: 2781)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S001000, C710S260000, C711S004000, C711S100000
Reexamination Certificate
active
06240470
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
The present invention relates to a technique applicable to a magnetic disk control unit intervening between a host unit and a magnetic disk unit for executing write/read control in/from the magnetic disk unit in accordance with an input/output signal from the host unit, and more particularly to a magnetic disk control unit incorporating an active-interchange function to interchange, or replace, firmwares during its operation on connection to the host unit, and a firmware active-interchange method to be conducted therein.
2) Description of the Related Art
With reference to
FIG. 10
, a description will be made hereinbelow of an arrangement of a common magnetic disk control unit and an arrangement of a system including that magnetic disk control unit. As shown in
FIG. 10
, between a CPU
10
serving as a host unit and a magnetic disk unit
30
, there is interposed a magnetic disk control unit (FCU: File Control Unit)
20
which takes charge of write/read control in/from the magnetic disk unit
30
according to an input/output signal (which will sometimes be referred hereinafter to as an I/O) from the CPU
10
.
This magnetic disk control unit
20
is composed of CAs (Channel Adapters)
21
, a cache memory
22
, DAs (Device Adapters)
23
, a CFE (Cache Function Engine)
24
, a RM (Resource Manager)
25
and a built-in disk
26
.
In this arrangement, the CAs
21
are respectively placed in channels for establishing connections between the CPU
10
and the magnetic disk control unit
20
, and as will be described herein later, are for conducting processing depending upon an I/O (interruption) from the CPU
10
or an interruption occurring within the magnetic disk control unit
20
. In the illustration of
FIG. 10
, as an example, four channels (paths) are provided between the CPU
10
and the magnetic disk control unit
20
.
The cache memory
22
is for temporarily storing data to be written from the CPU
10
into the magnetic disk unit
30
or data to be read out from the magnetic disk unit
30
to the CPU
10
, and is under control of the CFE
24
.
The DAs
23
are respectively put in paths for setting up connections between the magnetic disk control unit
20
and the magnetic disk unit
30
, and conduct access processing to the magnetic disk unit
30
, or perform processing for a response from the magnetic disk unit
30
in relation to that access.
FIG. 10
illustrates an example in which four paths are placed between the magnetic disk control unit
20
and the magnetic disk unit
30
.
The RM
25
acts to manage the whole magnetic disk control unit
20
comprising a plurality of functional modules (numerals
21
,
23
,
24
) mentioned above.
Each of the aforesaid CAs
21
, DAs
23
, CFE
24
and RM
25
is constructed as a firmware (for example, a microprogram fixedly put through a ROM or the like into a hardware).
The built-in disk
26
is for retaining firmwares constituting the CAs
21
, the DAs
23
, the CFE
24
and the RM
25
, which are written in ROMs on printed-circuit boards (CAs
21
, DAs
23
, CFE
24
and RM
25
) composing the magnetic disk control circuit
20
at the start of the magnetic disk control unit
20
. In addition, the built-in disk
26
is made to hold firmwares, for example, corresponding to four generations (four versions), and as will be mentioned herein later, is designed to exchange a firmware in use for a firmware held in this built-in disk
26
at the interchange between firmwares.
For the version-up to deal with functional changes, additions or the like in the above-mentioned magnetic disk control unit
20
, the interchange between firmwares has taken place. In a prior art, this firmware interchange has been done in the off-line condition between the CPU
10
and the magnetic disk control unit
20
, with the off-line condition being again switched to the on-line condition after the completion of the interchange. Accordingly, the off-line condition remains during the firmware interchange, thus interrupting the system.
However, recently, the system has frequently been required to operate for 24 hours, and therefore, to avoid the system interruption resulting from the off-line condition between the CPU
10
and the magnetic disk control unit
20
at the firmware interchange, there exists an expectation of being able to interchange firmwares without the occurrence of such an off-line condition (that is, while maintaining the on-line condition). Such an interchange to be conducted in a state where the on-line condition remains between the CPU
10
and the magnetic disk control unit
20
is called an active-interchange.
Secondly, a description will be taken hereinbelow of a prior firmware active-interchange method.
In the prior firmware active-interchange method, for accomplishing the firmware interchange in a state where the CPU
10
and the magnetic disk control unit
20
are in the on-line condition, a busy response (reply by a busy signal) takes place from the CAs
21
to the CPU
10
if an I/O comes in from the CPU
10
during the firmware interchange. In such a state, as will be mentioned herein later, a portion of the firmware constituting the CAs
21
is interchanged with the whole firmware (DAs
23
, CFE
24
and RM
25
) other than CAs
21
.
Although the magnetic disk control unit
20
having the active-interchange function for interchanging firmwares during an operation on the connection with the CPU
10
is basically constructed as shown in
FIG. 10
, in the magnetic disk control unit
20
with the active-interchange function, the CAs
21
are equipped with a busy response function acting during the firmware interchange. Such a firmware structure of the CAs
21
is shown in FIG.
11
.
A look at
FIG. 11
shows that the prior CAs
21
firmware involves an interruption control section
41
, an internal table area
42
and a firmware control section
43
.
The interruption control section
41
refers to the contents (a pointer table or the like) of the internal table area
42
in accordance with an interruption (interruption such as an I/O from the CPU
10
and a communication between functional modules in the magnetic disk control unit
20
), thereby advancing to an operation by a processing section (function) in the firmware control section
43
.
Furthermore, when an I/O comes in from the CPU
10
during the firmware interchange in the magnetic disk control unit
20
, the interruption control section
41
refers to the internal table area
42
and gives a busy signal as a reply to the CPU
10
, with the reply based on the busy signal being recorded in the internal table area
42
.
The internal table area
42
is for the purpose of keeping a variety of data the control needs, and includes a pointer table for indication of addresses of various kinds of functions and a variable table for retention of various kinds of variables for the firmware control section
43
. The variable table involves areas, such as (1) an area (a flag representative of that a firmware is in or under interchange, and others) for indicating the situation the firmware itself is presently placed in, (2) an area for storing whether or not a busy signal is given as a replay to the CPU
10
, (3) an area for maintaining a path for the connection with the CPU
10
and a physical connection condition, and (4) an area for retaining data for each of the magnetic disk units to be connected to the magnetic disk control unit
20
. In this case, the data held in the aforesaid areas (1) to (3) are required to surely exist before and after the firmware interchange.
The firmware control section
43
serves as an area to retain functions for the actual processing (access processing to, or proportionate to, an I/O, communications between functional modules, and others). For the function pointer control in the CAs
21
, the values corresponding to the offset positions of various kinds of functions retained in the firmware control section
43
are put in the pointer table of the internal table area
42
. Further, the interruption contro
Murai Katsumi
Murayama Takashi
Sakamoto Shigeru
Etienne Ario
Fujitsu Limited
Greer Burns & Crain Ltd
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