Macroscalar processor architecture

Details Macroscalar processor architecture Macroscalar processor architecture

2004-04-23

2008-07-01

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C717S160000

Reexamination Certificate

active

07395419

ABSTRACT:
A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that comprise a machine executable program. For each of the primary instructions received, at least one of the iteration units generates multiple secondary instructions that correspond to multiple loop iterations of the task of the respective primary instruction when executed by the one or more execution units. Other methods and apparatuses are also described.

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