Macrocell architecture with high speed product terms

Details Macrocell architecture with high speed product terms Macrocell architecture with high speed product terms

1995-09-26

1997-03-11

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

H03K 1700

Patent

active

056105363

ABSTRACT:
A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.

REFERENCES:
patent: 4758746 (1988-07-01), Birkner et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5309046 (1994-05-01), Steele
patent: 5350954 (1994-09-01), Patel
patent: 5362999 (1994-11-01), Chiang
"The Programmable Logic Data Book" copyright 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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