Macrocell and clock signal allocation circuit for a programmable

Details Macrocell and clock signal allocation circuit for a programmable Macrocell and clock signal allocation circuit for a programmable

1995-06-02

1996-12-31

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, H03K 19173

Patent

active

055897827

ABSTRACT:
Output logic macrocells for a programmable logic device (PLD) as well as a block clock/control circuit for use in the PLD to allocate multiple clock signals to each macrocell. Each macrocell includes a multiplexer selectively providing one of the multiple clock signals to a clock input of a storage element. The storage element additionally receives a sum of product terms output from an OR gate at its data input. The storage element is configured so that, depending on the clock input, it will function in a latch mode, a D-type flip-flop mode with either single edge or dual edge triggering, a combinatorial mode, a mixed clock mode, a reset mode, or a preset mode.

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