Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-11
2003-03-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06536030
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a macroblock that is treated as a single unit when designing the layout of a semiconductor integrated circuit, a storage medium for storing intellectual property, which is abbreviated as IP here on, including information on the macroblock, and a method of creating a layout for a semiconductor integrated circuit using the macroblock.
2. Description of the Prior Art
A conventional macroblock consists of a group of cells, each of which implements each of a plurality of functions. When configuring layers in the design of the layout of a semiconductor integrated circuit, at least a macroblock that constitutes the semiconductor integrated circuit is arranged and macrocells (or macroblocks) that are not associated with the former macroblock are connected to one another so that paths for connecting the macrocells to one another go around or over the former macroblock.
Referring next to
FIG. 10
, it illustrates a diagram showing the structure of a higher layout layer in which a conventional macroblock is disposed. In the figure, reference numeral
101
denotes the higher layout layer, numeral
102
denotes the conventional macroblock, and numeral
103
a
to
103
c
denote macrocells or macroblocks, which will be referred to as macrocell hereinafter for simplicity. The plurality of macrocells shown in
FIG. 10
have a net that is not connected to the macroblock
101
. Furthermore, reference numeral
104
denotes an output port of the first macrocell
103
a
for driving the net, numerals
105
b
and
105
c
denote respective input ports of the second and third macrocells
103
b
and
103
c
that are driven by the first macrocell, numeral
106
denotes a buffer that is inserted for improving the time delay caused between the output port
104
and the input port
105
, numeral
107
a
denotes a path for connecting the output port
104
of the first macrocell
103
for driving the net to the input terminal of the buffer
106
, and numeral
107
b
denotes a path for connecting the output terminal of the buffer
106
to the input ports
105
b
and
105
c
of the second and third macrocells
103
b
and
103
c
that are driven by the first macrocell.
Next, the description will be directed to the layout design of a semiconductor integrated circuit. When configuring a layer at a higher level using the conventional macroblock
102
, the plurality of macrocells
103
a
to
103
c
and the macroblock
102
are arranged in the higher layout layer
101
. The macroblock
102
includes no buffer used for improving the time delay caused between the plurality of macrocells
103
a
to
103
c
which are not associated with the macroblock
102
. Therefore, in the higher layout layer
101
the buffer
106
is additionally disposed outside the macroblock
102
. The paths
107
a
and
107
b
connect the output port
104
of the first macrocell
103
a
for driving the net, which is not connected to the macroblock
102
, by way of the buffer
106
, to the input ports
105
b
and
105
c
of the second and third macrocells that are driven by the first macrocell. The paths go around the macroblock
102
.
Since the buffer
106
is not disposed within the macroblock
102
, the paths
107
a
and
107
b
for connecting the output port
104
of the first macrocell
103
a
for driving the net, which is not connected to the macroblock
102
, to the input ports
105
b
and
105
c
of the second and third macrocells
103
b
and
103
c
that are driven by the first macrocell has to be wired so as to go around the macroblock
102
.
Japanese Patent Application Publication (TOKKAIHEI) No. 11-145292 discloses such a conventional macroblock, for example.
A problem that arises when designing the layout of a semiconductor integrated circuit using a conventional macroblock constructed as above is that when there is a need to insert a buffer or the like into a through path for connecting macrocells that are not associated with the macroblock with one another in order to improve the time delay caused between the macrocells, an additional buffer or the like has to be disposed outside the macroblock so as to connect the macrocells to one another because the macroblock includes no buffer, and, when the macrocells are arranged while facing with one another with the macroblock between, the through path for connecting the macrocells with one another has to be wired so as to go around the macroblock and the length of the through path is therefore increased. In particular, this tendency is strengthened when designing the top layout layer.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above problem. It is therefore an object of the present invention to provide a macroblock capable of reducing the length of wiring between macrocells disposed with facing with each other with the macroblock between, therefore speeding up a semiconductor integrated circuit using such a macroblock, reducing the power consumption, downsizing the semiconductor integrated circuit, and designing the layout and wiring of the semiconductor integrated circuit with efficiency.
It is a further object of the present invention to provide a storage medium for storing IP of the macroblock.
It is another object of the present invention to provide a method of creating a layout for a semiconductor integrated circuit using at least a macroblock, the method being capable of reducing the length of wiring between macrocells disposed outside the macroblock with facing with each other with the macroblock between.
In accordance with one aspect of the present invention, there is provided a macroblock that is treated as a single unit when creating a layout for a semiconductor integrated circuit, the macroblock comprising: at least a cell for implementing one or more functions which the macroblock has to perform; and a plurality of through path forming-cells each used for forming a through path passing through the macroblock, the plurality of through path forming cells being inserted into the macroblock in advance of creating a layout for a semiconductor integrated circuit so that they are spread over the macroblock in a predetermined way.
Preferably, each of the plurality of through path forming cells is a buffer. As an alternative, each of the plurality of through path forming cells is an inverter. Each of the plurality of through path forming cells can alternatively be a clock control cell for controlling a clock applied thereto. Preferably, each of the plurality of through path forming cells is a latch. As an alternative, each of the plurality of through path forming cells is a flip-flop.
Preferably, the plurality of through path forming cells include at least two types of components selected from among buffers, inverters, clock control cells for controlling a clock applied thereto, latches, and flip-flops.
In accordance with a preferred embodiment of the present invention, the macroblock further comprises a through path defined in the macroblock in advance of creating a layout for a semiconductor integrated circuit and connected to each of the plurality of through path forming cells, for establishing connection between cells disposed outside the macroblock.
In accordance with another preferred embodiment of the present invention, the macroblock further comprises a plurality of through path possibilities defined in the macroblock in advance of creating a layout for a semiconductor integrated circuit and connected to each of the plurality of through path forming cells, one of the plurality of through path possibilities being selected to establish connection between cells disposed outside the macroblock when creating a layout for a semiconductor integrated circuit.
In accordance with another aspect of the present invention, there is provided a computer-readable storage medium including an intellectual property or IP core, the IP code including: information on a macroblock used when creating a layout for a semiconductor integrated circuit; and information on a plurality of throu
Burns Doane , Swecker, Mathis LLP
Siek Vuthe
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