Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-15
2003-04-01
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06543040
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuits. More particularly, the present invention relates to pre-designing hard macros, or other hierarchically designed entities, within integrated circuits to accommodate a combination of subsequent stage wiring and circuit insertion across the macros.
BACKGROUND OF THE INVENTION
It is well-known that with increasing circuit densities, timing requirements, and bus capacities in integrated circuit chips wiring widths must be decreased. Decreased wiring widths, however, lead to increased resistances, impacting the slew rate and path delay of the wiring. Wiring must comply with a maximum slew rate and minimum delay based on the required timing. This wiring problem is aggravated when macro “blocks” occupy otherwise open space on the integrated circuit plan. These macros often interfere with subsequently-designed wiring paths which must comply with the slew rate and delay requirements.
To illustrate these problems, and with reference to
FIG. 1
, an IC
10
may include an embedded macro
12
having remnant silicon and/or wiring whitespace areas
24
1
, . . .
24
4
Assume that IC wiring is required from region
14
to region
16
of the IC. Running wiring across the macro may not be possible, since design tools usually see the macro as a fixed block, which cannot be modified when placing and routing the higher level IC wiring. Even assuming that whitespace is available and recognized by the design tools, running a standard width wire
18
across the macro may not suffice, since the distance over which this wire is run (i.e., the horizontal width of the macro
12
) may exceed that required for the maximum slew rate and delay.
Another option involves re-routing the wiring around the macro along the longer path
20
, and using repowering circuits
22
1
. . .
22
5
to maintain the required slew rate and path delays while compensating for the excess path length. This approach, however, involves the use of valuable silicon area and power to support the repowering circuits, and may not be sufficient to meet path delay requirements.
What is required, therefore, are techniques for maintaining the required wiring slew rates and path delays across an entire IC in the presence of large, fixed macro blocks.
SUMMARY OF THE INVENTION
The present invention addresses the above problems during the design of the macros themselves by preparing the macros for anticipated subsequent stage wiring. The wiring and/or silicon whitespace areas of the macro are designed to accommodate the wiring. In that regard, the present invention, in one aspect is related to a method, system and corresponding computer program products (program code and data structures) directed to designing an IC macro, across which subsequent stage wiring is expected to run. A macro destined for the IC is identified, within which whitespace is identified available to facilitate the subsequent stage wiring running across the macro. The whitespace within the macro is designed especially to accommodate the subsequent stage wiring running across the macro.
The design of the whitespace of the macro may include rearranging wiring whitespace within the macro into at least one routing track to accommodate the wiring. The routing track may extend from one side of the macro to another side thereof and, to provide for decreased resistances, a width of the routing track may be greater than the minimum wiring width of the IC.
During the design of the macro whitespace, silicon whitespace may also be rearranged into circuit areas, optionally corresponding to the rearranged wiring whitespace. The presence of these circuit areas is conveyed through the design process to subsequent stage design, during which active circuits can be “dropped in” to these areas to support the subsequent stage wiring.
The whitespace of the macro may also include shielding to shield the wiring from areas of the macro bounding the whitespace. In one particularly unique embodiment of the present invention, the shielding comprises macro power bussing and/or macro wiring arranged to simultaneously effect shielding.
Other options for designing the macro whitespace to accommodate the subsequent stage wiring include, for example, designing power bussing in the whitespace for support circuits for the subsequent stage wiring. At least one active circuit may be designed into the whitespace to repower a signal within the wiring. For active circuits, pin areas are also designed in the macro for connection to the active circuit and for connection to the wiring, such that chip level design tools can connect the subsequently placed wiring to these accessible pins. The active circuits may be, e.g., repowering buffers or inverters.
In accordance with the present invention, by specially designing the whitespace of the macro to accommodate this subsequent stage wiring, including optional shielding, power bussing and/or active circuits, wiring can be effectively routed across the macro without adverse effects on the slew rate or path delay.
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Kurdahi, F.J, et al., “Techniques for area estimation of VLSI layouts”, IEEE, Jan. 1989. pp. 81-92.
Bednar Thomas R.
Dunn Paul E.
Gould Scott W.
Panner Jeannie H.
Zuchowski Paul S.
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Niebling John F.
Radigan, Esq. Kevin P.
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