Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-05-20
2008-05-20
Lamarre, Guy J. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C370S335000, C370S342000, C370S394000, C370S441000
Reexamination Certificate
active
07376879
ABSTRACT:
A medium access control (MAC) architecture determines transmission latency and block error rate requirements for a plurality of data flows, each data flow having an associated priority and each data flow comprising a plurality of data blocks. The MAC architecture specifies a scheduling entity that determines when transmissions are serviced, and by which hybrid automatic repeat request (H-ARQ) entity. H-ARQ entities determine whether each prior block had been successfully transmitted and, if not, request retransmission of unsuccessfully transmitted data blocks. The scheduling of the data blocks takes into account whether or not the previously transmitted data blocks require retransmission. The MAC architecture allows the scheduling entity the ability to initiate new transmissions at any time and to reinitiate previously unsuccessful transmissions at any time.
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Bolourchi Nader
Terry Stephen E.
InterDigital Technology Corporation
Lamarre Guy J.
Volpe and Koenig P.C.
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