M/A for optimizing retry time upon cache-miss by selecting a del

Details M/A for optimizing retry time upon cache-miss by selecting a del M/A for optimizing retry time upon cache-miss by selecting a del

1995-10-02

1997-09-02

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711169, 711143, 711144, G06F 1316

Patent

active

056641540

ABSTRACT:
A single dirty bit is maintained in a memory controller for each cache line of a cached memory system using a cache write-back policy. The dirty bit is set after each write access, is reset after each read access in which a cache miss occurs, and is left unchanged after all other memory accesses. The dirty bit is used to select a delay value for submitting a retry request packet after a cache miss occurred in a memory access. The delay value minimizes memory access time by allowing for a write-back operation only when necessary.

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