M&A for exchanging date, status and commands over an hierarchica

Details M&A for exchanging date, status and commands over an hierarchica M&A for exchanging date, status and commands over an hierarchica

1997-12-01

1999-06-01

Auve, Glenn A.

395309, G06F 1300

Patent

active

059095563

ABSTRACT:
Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

REFERENCES:
patent: 5341480 (1994-08-01), Wasserman et al.
patent: 5694555 (1997-12-01), Morriss et al.
ARCNET Local Area Network Standard ATA/ANSI 878.1, Version 1.9, ARCNET Trade Association, 1992.
High Performance Serial Bus, P1394/Draft 6.2v0, IEEE, Jun. 1, 1993.

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