Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-02
2004-04-13
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S141000, C257S162000
Reexamination Certificate
active
06720624
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a new ESD protection structure. More particularly, it relates to a LVTSCR-like structure with high holding voltage, for protecting CMOS and Bi-CMOS integrated circuits against electrostatic discharge and electrical overstress.
BACKGROUND OF THE INVENTION
Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. Clamps have been devised to shunt current to ground during excessive voltage peaks.
One of the difficulties encountered in designing such protection circuitry is that the specifications for these clamps have to fit within a relatively small design window that, on the one hand, must take into account the breakdown voltage of the circuit being protected, and, on the other hand, avoid latch-up under normal operation. ESD clamps are designed to handle short voltage peaks and are not suitable for sustained high voltages. They therefore have a holding voltage parameter below which they are sustainable under non-ESD conditions. Thus, the clamp must be designed so as to be activated below the breakdown voltage of the circuit that is to be protected. At the same time, the clamps holding voltage must exceed the normal operating voltage of the protected circuit, to avoid latch-up.
A wide variety of ESD protection structures have been devised, each with different characteristics. For example, some protection clamps employ avalanche diodes such as zener diodes to provide the bias voltage for the base of a subsequent power bipolar junction transistor (BJT). Another device that has been used is the grounded gate NMOS device (GGNMOS). However, GGNMOS devices are not only large, consuming a lot of space on a chip, they also suffer from the disadvantage that they support only limited current densities. The protection capability of an ESD protection device can be defined as the required contact width of the structure required to protect against an ESD pulse amplitude, or, stated another way, as the maximum protected ESD pulse amplitude for a given contact width. Thus, the smaller the contact width for a given ESD pulse amplitude protection, the better.
A commonly used protection clamp, especially for CMOS and BiCMOS circuits, therefore, makes use of a low voltage silicon controlled rectifier (LVTSCR). These support approximately 10 times more pulse power after snapback than do GGNMOS devices. However, they suffer from the drawback that they display low holding voltages. Thus they experience latch-up if the voltage after the ESD event does not return to a voltage lower than the holding voltage. As a result they are typically only used in power clamp applications.
However, it would be desirable to be able to use LVTSCRs in CMOS technology in so-called overvoltage cells. Overvoltage cells make use of cascoded structures in order to provide sufficiently large voltage drops to avoid gate breakdown. (In one process —CMOS
9
DGO by National Semiconductor—5.5V cells have a gate breakdown of approximately 4V) The major limitation to the use of LVTSCRs in such applications is the low holding voltage of about 2V, which creates latch-up problems.
The present invention seeks to address this problem by providing a LVTSCR-like structure with higher holding voltage. For ease of understanding, it is useful to look at the structure and workings of a conventional LVTSCR.
A low voltage silicon-controlled rectifier (LVTSCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a trigger voltage. When the voltage across the first and second nodes rises to be equal to or greater than the trigger voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the trigger voltage. When used for ESD protection, the first node becomes a to-be-protected node, and the second node is typically connected to ground. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node.
Thus, when the voltage across the to-be-protected node and the second node is less than the trigger voltage, the LVTSCR provides an open circuit between the to-be-protected node and the second node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body discharge occurs, the LVTSCR provides a low-resistance current path from the to-be-protected node to the second node. In addition, once the ESD event has passed the voltage on the to-be-protected node has to again fall below the holding voltage for the LVTSCR to again provide an open circuit between the to-be-protected node and the second node.
FIG. 1
shows a cross-sectional diagram that illustrates a conventional LVTSCR
100
. The LVTSCR
100
has a n-well
112
formed in a p-type material
110
. n+ and p+ regions are formed in each of the n-well
112
and the p-material
110
. In the case of the n-well
112
the regions include n+ region
114
and p+ region
116
. For the p-material
110
, the regions are n+ region
122
and p+ region
124
. Furthermore, a n+ (drain) region
130
is formed in both material
110
and n-well
112
, and a channel region
132
is defined between n+ (source) region
122
and n+ (drain) region
130
. In addition, LVTSCR
100
includes a gate
136
. N+ (source and drain) regions
122
,
130
, and gate
136
define a NMOS transistor
138
which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10-15 volts.
Since NMOS transistor
138
is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region
130
and material
110
breaks down at the same time that the to-be-protected MOS transistors experience junction breakdown, thereby preventing destructive breakdown of the MOS transistors that are being protected.
In operation, when the voltage across node
120
(low voltage node) and
126
(high voltage node) is positive and less than the trigger voltage, the voltage reverse biases the junction between n-well
112
and p-type material
110
. The reverse-biased junction, in turn, blocks charge carriers from flowing from node
120
to node
126
. However, when the voltage across nodes
120
and
126
is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into material
110
, and a large number of electrons to be injected into n-well
112
. The increased number of holes increases the potential of material
110
in the region that lies adjacent to n+ region
122
, and eventually forward biases the junction between material
110
and n+ region
122
.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region
122
as the emitter, p-type material
110
as the base, and n-well
112
as the collector turns on. When turned on, n+ (emitter) region
122
injects electrons into (base) material
110
. Most of the injected electrons diffuse through (base) material
110
and are swept from (base) materi
Beek Marcel ter
Concannon Ann
Hopper Peter J.
Vashchenko Vladislav
Jackson Jerome
National Semiconductor Corporation
Vollrath Jurgen
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